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The Trenz Electronic TE0745 is an industrial-grade SoC module integrating a Xilinx Zynq-7 (Z-7030, Z-7035 or Z-7045), 1 GByte DDR3/L SDRAM, 32 MByte SPI Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips.

Block Diagram

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Figure 1: TE0745-02 Block Diagram

Main Components

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Figure 2: TE0745-02 SoC module

1. Xilinx ZYNQ-7000 family SoC, U1
2. 256 Mbit Quad SPI Flash Memory Micron N25Q256A, U12
3. Reference clock signal oscillator SiTime SiT8008BI @33.333 MHz, U12
4. Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U9
5. Marvell Alaska 88E1512 Gigabit Ethernet PHY, U3
6. Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16 Bit Word-Width), U3
7. TI TPS51206 DDR3 Memory Termination Regulator with buffered reference votlage VTTREF, U18
8. Intersil ISL12020MIRZ Real-Time-Clock, U24
9. TI TCA9517 Level-shifting I²C bus repeater, U17
10. LED D2 red
    
11. LED D1 green
12. Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16 Bit Word-Width), U5
13. Altera Enpirion EN63A0QI 12A DCDC PowerSoC @1.0V (VCCINT), U4
    
14. TI TPS74401RGW LDO DC/DC regulator @1.2V (MGTAVTT), U8
15. TI TPS72018DRVR LDO DC/DC regulator @1.8V (MGTAUX), U6
16. TI TPS74401RGW LDO DC/DC regulator @1.0V (MGTAVCC), U11
17. Silicon Labs Si5338A I²C Programmable Quad Clock Generator, U13
18. Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U21
19. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J3
20. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J1
21. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J2
22. 256 Mbit Quad SPI Flash Memory (Micron N25Q256A, U14
23. Microchip USB3320 USB Transceiver PHY , U32
24. Reference clock signal oscillator SiTime SiT8008BI @52.000 MHz, U33
25. Microchip 24AA025E48 EEPROM for MAC Address
26. Lattice Semiconductor MachXO2-256HC System Controller CPLD, U2
    

Key Features

• Industrial-grade Xilinx Zynq-7000 (Z-7030, Z-7035, Z-7045) SoC module

• Rugged for shock and high vibration
• 10/100/1000 Mbps Ethernet transceiver PHY
• EEPROM for storing Ethernet MAC Address
• 16-Bit wide 1GB DDR3 SDRAM
• 32 MByte QSPI flash memory
• Programmable clock generator
• Plug-on module with 3 × 160-pin high-speed hermaphroditic strips
• 132 FPGA I/Os (65 LVDS pairs possible) and 14 PS MIO available on B2B connectors
• 8 GTX (high-performance transceiver) lanes
• USB 2.0 OTG high-speed PHY
• On-board high-efficiency DC-DC converters
• System management
• eFUSE bit-stream encryption
• AES bit-stream encryption
• Temperature compensated RTC (real-time clock)
• User LED
• Evenly-spread supply pins for good signal integrity

Additional assembly options are available for cost or performance optimization upon request.

Initial Delivery State

Key Features

• Industrial-grade Xilinx Zynq-7000 (Z-7030, Z-7035, Z-7045) SoC module

• Rugged for shock and high vibration
• 10/100/1000 Mbps Ethernet transceiver PHY
• EEPROM for storing Ethernet MAC Address
• 16-Bit wide 1GB DDR3 SDRAM
• 32 MByte QSPI flash memory
• Programmable clock generator
• Plug-on module with 3 × 160-pin high-speed hermaphroditic strips
• 132 FPGA I/Os (65 LVDS pairs possible) and 14 PS MIO available on B2B connectors
• 8 GTX (high-performance transceiver) lanes
• USB 2.0 OTG high-speed PHY
• On-board high-efficiency DC-DC converters
• System management
• eFUSE bit-stream encryption
• AES bit-stream encryption
• Temperature compensated RTC (real-time clock)
• User LED
• Evenly-spread supply pins for good signal integrity

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Image Added

Figure 1: TE0745-02 Block Diagram

Main Components

            Image Added               Image Added

Figure 2: TE0745-02 SoC module

1. Xilinx ZYNQ-7000 family SoC, U1
2. 256 Mbit Quad SPI Flash Memory Micron N25Q256A, U12
3. Reference clock signal oscillator SiTime SiT8008BI @33.333 MHz, U12
4. Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U9
5. Marvell Alaska 88E1512 Gigabit Ethernet PHY, U3
6. Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16 Bit Word-Width), U3
7. TI TPS51206 DDR3 Memory Termination Regulator with buffered reference votlage VTTREF, U18
8. Intersil ISL12020MIRZ Real-Time-Clock, U24
9. TI TCA9517 Level-shifting I²C bus repeater, U17
10. LED D2 red
    
11. LED D1 green
12. Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16 Bit Word-Width), U5
13. Altera Enpirion EN63A0QI 12A DCDC PowerSoC @1.0V (VCCINT), U4
    
14. TI TPS74401RGW LDO DC/DC regulator @1.2V (MGTAVTT), U8
15. TI TPS72018DRVR LDO DC/DC regulator @1.8V (MGTAUX), U6
16. TI TPS74401RGW LDO DC/DC regulator @1.0V (MGTAVCC), U11
17. Silicon Labs Si5338A I²C Programmable Quad Clock Generator, U13
18. Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U21
19. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J3
20. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J1
21. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J2
22. 256 Mbit Quad SPI Flash Memory (Micron N25Q256A, U14
23. Microchip USB3320 USB Transceiver PHY , U32
24. Reference clock signal oscillator SiTime SiT8008BI @52.000 MHz, U33
25. Microchip 24AA025E48 EEPROM for MAC Address
26. Lattice Semiconductor MachXO2-256HC System Controller CPLD, U2
    

Initial Delivery State

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On-board LEDs

Table 8: LEDs of the SoC module

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The SoC module has the following sources to be provided with extern reference clock signals and on-board clock oscillators:

Table 12: Clock sources overview

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Table 6: Ethernet PHY interface connections

MAC Address EEPROM

A Microchip 24AA025E48 EEPROM (U23) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I²C slave address 0x53.

USB Interface

USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an on-board 25 MHz oscillator (U15).

USB Interface

USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an on-board 25 MHz oscillator (U15).

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Boot Process

RTC - Real Time Clock

An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I²C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at I²C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to The Zynq-module TE0745 supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 31, pin 421.

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The Zynq-module TE0745 supports different boot modes which are configurable by the current boot mode will be set by the MIO-pins MIO3...MIO5. The control line 'BOOTMODE' and ' is connected to the 'MIO4' pin, 'BOOTMODE_1' . The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21.The current boot mode will be set by the MIO-pins MIO3...MIO5. The control line 'BOOTMODE' is connected to the 'MIO4' pin, 'BOOTMODE_1' to 'MIO5'to 'MIO5'.

Following table describes how to set the control lines to configure the desired boot mode:

Table 9: Selectable boot modes

On-board Peripherals

Processing System (PS) Peripherals

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Table 9: Selectable boot modes

On-board Peripherals

Flash

MAC Address EEPROM

A Microchip 24AA025E48 EEPROM (U23) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I²C slave address 0x53.

RTC - Real Time Clock

An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I²C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at I²C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD on bank 3, pin 4.

Programmable PLL Clock (Phase-Locked Loop)

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See Xilinx datasheet DS191 for additional information. User should also check related base board documentation when intending base board design for TE0745 module.

Power Rails

Table 15: Power rails of the SoC module on accessible connectors

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Technical Specification

Absolute Maximum Ratings

Recommended Operating Conditions

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Figure 5: TE0745 SoC module revision number

Document Change History 

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