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| Pin Name | Mode | Function | B2B Connector Pin | Default Configuration | ||
|---|---|---|---|---|---|---|
| JTAG_EN | Input | JTAG Select | J1-148 |
At normal operation the JTAG-signals will be forwarded to the SoC module. VCCIO: PS_3.3V | ||
| RST_IN_N | Input | Reset | J2-131 | Low-active Power-On reset pin, controls POR_B-signal (bank 500, pin C23) of Zynq-chip. | ||
| PS_SRST | Input | Reset | J2-152 | Low-active PS system-reset pin of Zynq-chip. | ||
| BOOTMODE | InputOutput | Bootmode | J2-133 | Control line which sets in conjunction with signal 'BOOTMODE1' (B2B-pin J2-133) Permanent logic high in standard SC-CPLD firmware. | ||
| PWR_PL_OK | OutputInput | Power Good | J2-135 | Indicates stable state of PL supply voltage (low-active) after power-up sequence. | ||
| PWR_PS_OK | OutputInput | Power Good | J2-139 | Indicates stable state of PS supply voltage (low-active) after power-up sequence. | ||
| EN_PL | Output | Enable-signal | - | Low active Enable-signal for activating PL supply voltage. Permanent logic high in standard SC-CPLD firmware. | ||
| MIO8 | Input/Output | PS MIO | - | User I/O (pulled-up to PS_1.8V) | ||
| MIO0 | Input/Output | PS MIO | J2-137 | User I/O | ||
| RTC_INT | Input | Interrupt-signal | - | Interrupt-signal from on-board RTC | ||
| LED | Output | LED control | - | Green LED D1, indicates SC-CPLD activy by blinking |
On-board LEDs
| LED | Color | connected to | Description and Notes |
|---|---|---|---|
D1 | Green | SC CPLD, bank 3, pin 5 | System main status LED, blinking frequently or at system activity |
D2 | Red | Zynq-Chip (U1), bank 0 (config bank), 'DONE' (pin W9) | Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured. This LED will not operate if the SC CPLD can not power up the PL supply voltage. |
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