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  1. Xilinx ZYNQ-7000 family SoC, U1
  2. 256 Mbit Quad SPI Flash Memory memory Micron N25Q256A, U12
  3. Reference clock signal oscillator SiTime SiT8008BI @33.333 MHz, U12
  4. Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U9
  5. Marvell Alaska 88E1512 Gigabit Ethernet PHY, U3
  6. Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16 Bit Word-Widthbit word width), U3
  7. TI TPS51206 DDR3 Memory Termination Regulator memory termination regulator with buffered reference votlage voltage VTTREF, U18
  8. Intersil ISL12020MIRZ Real-Time-Clock, U24
  9. TI TCA9517 Levellevel-shifting I²C I2C bus repeater, U17
  10. Red LED, D2 red
  11. Green LED, D1 green
  12. Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks banks a 32 MWords, 16 Bit Word-Width), U5
  13. Altera Enpirion EN63A0QI 12A DCDC DC-DC PowerSoC @1.0V (VCCINT), U4
  14. TI TPS74401RGW LDO DC/-DC regulator @1.2V (MGTAVTT), U8
  15. TI TPS72018DRVR LDO DC/-DC regulator @1.8V (MGTAUX), U6
  16. TI TPS74401RGW LDO DC/-DC regulator @1.0V (MGTAVCC), U11
  17. Silicon Labs Si5338A I²C I2C Programmable Quad Clock Generator, U13
  18. Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U21
  19. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J3
  20. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J1
  21. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J2
  22. 256 Mbit Quad SPI Flash Memory memory (Micron N25Q256A, U14
  23. Microchip USB3320 USB Transceiver transceiver PHY , U32
  24. Reference clock signal oscillator SiTime SiT8008BI @52.000 MHz, U33
  25. Microchip 24AA025E48 EEPROM for MAC Addressaddress, U23
  26. Lattice Semiconductor MachXO2-256HC System Controller CPLD, U2

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Storage device name

Content

Notes

24AA025E48 EEPROM

User content not programmed

Valid MAC Address from manufacturer.

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor.

SPI Flash Quad Enable bit

Programmed

-

SPI Flash main array

Demo design

-

eFUSE USER

Not programmed

-

eFUSE Security

Not programmed

-
Si5338 OTP NVMDefault settings pre programmedOTP not reprogrammable re-programmable after delivery from factory

...

The connector supports single ended and differential signaling as the I/O's are usable as LVDS - pairs.

The I/O signals are routed from the SoC's PL banks as LVDS - pairs to the B2B connectors.

BankTypeB2B ConnectorI/O Signal CountLVDS Pairs CountVCCO Bank VoltageNotes
12HRJ15024VCCIO_12
pins J1-54, J1-55		supported voltages from 1.2V to 3.3V
13HRJ15024VCCIO_13
pins J1-112, J1-113		supported voltages from 1.2V to 3.3V
33HPJ35024VCCIO_33
pins J3-115, J3-120		supported voltages from 1.2V to 1.8V
34HPJ25024VCCIO_34
pins J2-29, J2-30		supported voltages from 1.2V to 1.8V
35HPJ25024VCCIO_35
pins J2-87, J2-88		supported voltages from 1.2V to 1.8V
500MIOJ25-1.8V-
501MIOJ312-1.8V-

Table 2:   B2B connector pin-outs of available PL and PS banks of the SoC module

...

The B2B connector J1 and J2 provide also access to the MGT - banks of the SoC module. There are 8 high-speed data lanes (Xilinx GTX transceiver) available composed as differential signaling pairs for both directions (RX/TX).

The MGT - banks have also clock input-pins which are exposed to the B2B connector J3. Following MGT - lanes are available on the B2B connectors:

...

Pin NameModeFunctionB2B Connector PinDefault Configuration
JTAG_ENInputJTAG SelectJ1-148
Note
JTAG_EN pin in B2B connector J1-148 should be kept low or grounded for normal operation!

At normal operation the JTAG - signals will be forwarded to the SoC module.
Else the JTAG_EN pin must be high or open to update the CPLD firmware via JTAG - interface.

VCCIO: PS_3.3V

RST_IN_NInputResetJ2-131Low-active Power-On reset pin, controls POR_B-signal (bank 500, pin C23) of Zynq - chip.
PS_SRSTInputResetJ2-152Low-active PS system-reset pin of Zynq - chip.
BOOTMODEOutputBootmodeBoot modeJ2-133

Control line which sets in conjunction with signal 'BOOTMODE1' (B2B-pin J2-133)
the boot source of the Zynq - chip. See section "Boot Modes".

Permanent logic high in standard SC-CPLD firmware.

PWR_PL_OKInputPower GoodJ2-135Indicates stable state of PL supply voltage (low-active) after power-up sequence.
PWR_PS_OKInputPower GoodJ2-139Indicates stable state of PS supply voltage (low-active) after power-up sequence.
EN_PLOutputEnable-signal-

Low active Enable-signal for activating PL supply voltage.

Permanent logic high in standard SC-CPLD firmware.

MIO8InputPS MIO-User I/O (pulled-up to PS_1.8V)
MIO0InputPS MIOJ2-137User I/O
RTC_INTInputInterrupt-signal-Interrupt-signal from on-board RTC
LEDOutputLED control-Green LED D1, indicates SC-CPLD activy activity by blinking

Table 5: B2B connector pin-out of SC - CPLD 's I/O-pins

On-board LEDs

LEDColorconnected toDescription and Notes

D1

Green

SC CPLD, bank 3, pin 5System main status LED, blinking frequently or at system activity

D2

Red

Zynq-Chip (U1), bank 0 (config bank), 'DONE' (pin W9)

Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured.

This LED will not operate if the SC CPLD can not power up the PL supply voltage.

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Clock sourceSchematic nameFrequencyClock input destinationNote
B2B connector J3, pin J3-74/J3-76

CLKIN_N, CLKIN_P

userQuad PLL clock Generator U16, pin 1/2-
B2B connector J3, pin J3-75/J3-77

MGT_CLK0_P, MGT_CLK0_N

userMGT - bank 112, pin R6/R5-
B2B connector J3, pin J3-81/J3-83MGT_CLK2_P, MGT_CLK2_NuserMGT - bank 111, pin W6/W5-
SiTime SiT8008BI oscillator, U21-25.000 MHzQuad PLL clock Generator U16, pin 3-

SiTime SiT8008BI oscillator, U12

PS_CLK33.333 MHzBank 500 (MIO0 bank), pin B24-
SiTime SiT8008BI oscillator, U23OTG-RCLK52.000 MHzUSB 2.0 Transceiver PHY U32, pin 26-
SiTime SiT8008BI oscillator, U9ETH_CLKIN25.000 MHzGbit Ethernet PHY U7, pin 34-

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MIOFunctionConnected toNotes MIOFunctionConnected toNotes
0GPIOJ2-137, SC CPLD bank 2, pin 14user I/O on B2B 16..27ETH0Ethernet PHY U7RGMII
1QSPI0QSPI Flash Memory U14, pin C2SPI Flash-CS 28..39USB0USB PHY U32ULPI
2QSPI0QSPI Flash Memory U14, pin D3SPI Flash-DQ0 40GPIOJ2-150user I/O on B2B
3QSPI0QSPI Flash Memory U14, pin D2SPI Flash-DQ1 41GPIOJ2-152user I/O on B2B
4QSPI0QSPI Flash Memory U14, pin C4SPI Flash-DQ2 42GPIOJ2-154user I/O on B2B
5QSPI0QSPI Flash Memory U14, pin D4SPI Flash-DQ3 43GPIOJ2-156user I/O on B2B
6QSPI0QSPI Flash Memory U14, pin B2SPI Flash-SCK 44GPIOJ2-158user I/O on B2B
7GPIOUSB PHY U32, pin 27Low active USB PHY Reset (pulled-up to PS_1.8V) 45GPIOJ2-160user I/O on B2B
8GPIOSC CPLD bank 2, pin 13user I/O (pulled-up to PS_1.8V)
 46GPIOJ2-145

user I/O on B2B

9GPIOEthernet PHY U7, pin 16Ethernet PHY Reset 47GPIOJ2-147user I/O on B2B
10I²C SCL - line I²CI2C-interface1.8V ref. voltage 48GPIOJ2-149user I/O on B2B
11I²C SDA - line I²CI2C-interface1.8V ref. voltage 49GPIOJ2-151user I/O on B2B
12GPIOJ2-123user I/O on B2B 50GPIOJ2-153user I/O on B2B
13GPIOJ2-125user I/O on B2B 51GPIOJ2-155user I/O on B2B
14GPIOJ2-127user I/O on B2B 52ETH0USB PHY U32, pin 7MDC
15GPIOJ2-129user I/O on B2B 53ETH0USB PHY U32, pin 8MDIO

...

Table 11:  Module's I²C-interfaces overview

Boot Process

The Zynq-TE0745 module TE0745 supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21.

The current boot mode will be set by the MIO - pins MIO3...MIO5. The control line 'BOOTMODE' is connected to the 'MIO4' pin, 'BOOTMODE_1' to 'MIO5'.

...

Once running, the frequency and other parameters can be changed by programming the device using the I²C-bus connected between the Zynq - module (master) and reference clock signal generator (slave).

Si5338A (U13) inputsignal schematic nameNote

IN1/IN2

CLKIN_P, CLKIN_N

reference clock signal from B2B connector J3, pin J3-74/J3-76

(base board decoupling capacitors and termination resistor necessary)

IN3

reference clock signal from oscillator SiTime  SiT8008BI (U21)

25.000 MHz fixed frequency

IN4/IN6

pins put to GNDLSB (pin 'IN4') of the default I²C-adress 0x70 not activated

IN5

not connected

-
Si5338A (U13) output
signal schematic nameNote

CLK0 A/B

MGTCLK1_P, MGTCLK1_N

reference clock signal to MGT - bank 112, pin U6/U5

(100 nF decoupling capacitors)

CLK1 A/B

CLK1_P, CLK1_N

clock signal routed to B2B connector, pin J3-80/J3-82

CLK2 A/B

CLK2_P, CLK2_N

clock signal routed to B2B connector, pin J3-86/J3-88

CLK3 A/B

MGTCLK3_P, MGTCLK3_N

reference clock signal to MGT - bank 111, pin AA6/AA5

(100 nF decoupling capacitors)

...

The on-board voltages of the TE0745 SoC module will be powered-up in order of a determined sequence after the external voltages 'PL_VIN', 'PS_VIN' and 'PS_3.3V' are available.

Warning
To avoid any demages damage to the SoC module, check for stabilized on-board voltages in steady state before powering up the SoC's I/O bank voltages VCCO_x.

...

Parameter

MinMax

Units

Notes

PL_VIN-0.35VTI TPS720 data sheet
PS_VIN-0.37VTI TPS82085 data sheet
PS_3.3V3.1353.465V

3.3V nominal ± 5%

Attention: PS_3.3V is directly connected to numerous
on-board peripherals as supply and I/O voltage.

VBAT supply voltage-16.0VISL12020MIRZ data sheet
PL IO bank supply voltage for HR
I/O banks (VCCO)		-0.53.6V-

PL IO bank supply voltage for HP
I/O banks (VCCO)

-0.52.0V-
I/O input voltage for HR I/O banks-0.4VCCO_X+0.55V-
I/O input voltage for HP I/O banks-0.55VCCO_X+0.55V-
GT receiver (RXP/RXN) and transmitter (TXP/TXN)-0.51.26V-

Voltage on module JTAG pins

-0.33.6

V

MachX02 Family data sheet

Storage temperature

-40

+85

°C

limited from ISL12020MIRZLimits of ISL12020MIRZ RTC chp.
Storage temperature without the ISL12020MIRZ-55+100°Climit Limits of DDR3 memory chips.
Note
Assembly variants for higher storage temperature range are available on request.

...

ParameterMinMaxUnitsNotesReference Document
PL_VIN3.34.5V-TI TPS720 data sheet
PS_VIN3.36.0V-TI TPS82085 data sheet
PS_3.3V3.1353.465V-3.3V nominal ± 5%
VBAT_IN supply voltage2.75.5V-ISL12020MIRZ data sheet

PL I/O bank supply voltage for HR
I/O banks (VCCO)

1.143.465V-Xilinx datasheet DS191

PL I/O bank supply voltage for HP
I/O banks (VCCO)

1.141.89V-Xilinx datasheet DS191
I/O input voltage for HR I/O banks-0.20VCCO_X+0.20V-

Xilinx datasheet DS191

I/O input voltage for HP I/O banks-0.20VCCO_X+0.20V

-

Xilinx datasheet DS191
GT receiver (RXP/RXN) and transmitter (TXP/TXN)(*)(*)V(*) Check datasheetXilinx datasheet DS191
Voltage on Module JTAG pins3.1353.6VJTAG - signals forwarded to
Zynq - module config bank 0		MachX02 Family Data Sheet

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Note
Please check Xilinx datasheet DS191 (for XC7Z030) for complete list of absolute maximum and recommended operating ratings.

...

Figure 4: Physical dimensions of the TE0745 SoC module

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

24 g - Plain module

Revision History

...

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Figure 5: TE0745 SoC module revision number

Document Change History 

 Date

Revision

ContributorsDescription
2017-03-31
Ali Naseri, Jan Kumannfirst First TRM release.
2017-02-05
V1

 

Jan KumannInitial document.

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