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Table of Contents
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Overview
The Trenz Electronic TEF1001 FPGA board is a PCI Express form factor card (PCIe 2.0 or higher) integrating the Xilinx Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA SoC. The FPGA-board is designed for high system resources and intended for use in applications with high demands on system performance and throughput. To extent the board with standard DDR3 SDRAM memory module, there is a 204-pin SODIMM socket with 64bit databus width on the board present.
The board offers a HPC (High Pin Count) ANSI/VITA 57.1 compatible FMC interface connector for standard FPGA Mezzanine cards and modules. Other interface connectors found on-board include JTAG for accessing FPGA and on-board System Controller CPLD, and also connector with 5 high-speed I/O differential signaling pairs.
The TEF1001 FPGA board is intended to be used as add-on card in a PCIe 2.0 or higher capable host systems, it can not be used as a stand-alone device.
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Refer to http://trenz.org/tef1001-info for the current online version of this manual and other available documentation.
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Key Features
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- 16 GTX high-performance transceiver
- 2x MGT transceiver clock inputs
- 254 FPGA HR I/O's (125 LVDS pairs)
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- FPGA
- JTAG port (SPI indirect, bus width x4)
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- JTAG connector
- Quad SPI Flash memory
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Table of Contents
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Overview
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The Trenz Electronic TEF1001 FPGA board is a PCI Express form factor card integrating the Xilinx Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA SoC. The FPGA-board is designed for high system resources and intended for use in applications with high demands on system performance and throughput. To extent the board with standard DDR3 SDRAM memory module, there is a 204-pin SODIMM socket with 64bit databus width on the board present. Highspeed data transmission is enabled by the 4 lane PCIe Gen 2 interface.
The board offers a HPC (High Pin Count) ANSI/VITA 57.1 compatible FMC interface connector for standard FPGA Mezzanine cards and modules. Other interface connectors found on-board include JTAG for accessing FPGA and on-board System Controller CPLD.
The TEF1001 FPGA board is intended to be used as add-on card in a PCIe 2.0 or higher capable host system to meet the power supply requirements.
Refer to http://trenz.org/tef1001-info for the current online version of this manual and other available documentation.
Key Features
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- Xilinx Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA SoC
- Large number of configurable I/Os are provided via HPC FMC connector
- 4 GTX high-performance transceiver
- 2x MGT transceiver clock inputs
- 160 FPGA I/O's (80 LVDS pairs)
- On-board high-efficiency switch-mode DC-DC converters
- Lattice MachXO2 LCMXO2-1200HC System Controller CPLD
- 10x User LEDs
- PCI Express x8 connector with 4 lane PCIe Gen 2 interface
- ANSI Vita 57.1 FMC High Pin Count (HPC) connector
- DDR3 SODIMM SDRAM with ECC socket with 64bit databus width
- 256Mbit (32MByte) Quad SPI Flash memory (for configuration and operation) accessible through:
- FPGA
- JTAG port (SPI indirect, bus width x4)
- FPGA configuration through:
- JTAG connector
- Quad SPI Flash memory
Clocking
Si5338 programmable quad PLL clock generator - 4 outputs for MGT and PL clocks
200MHz oscillator for DDR3 bank
- System management and power sequencing
Additional assembly options are available for cost or performance optimization upon request.
Block Diagram
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Main Components
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- Xilinx Kintex XC7K-2FBG676I FPGA SoC, U6
- ANSI/VITA 57.1 compliant FMC HPC connector, J2
- Cooling fan 5VDC M1 (45X5MM, 0.7W, 1.06CFM), M1
- PCIe x8 connector, J1
- DDR3 SODIMM 204-pin socket, U2
- 6-pin 12V power connector, J5
- Step-down DC-DC converter @1.5V and @4V (LT LTM4676A), U3
- Step-down DC-DC converter @1.0V (LT LTM4676A), U4
- 256 Mbit Quad SPI Flash Memory (Micron N25Q256A), U12
- 10x Green user LEDs connected to FPGA, D1 ... D10
- 4-wire PWM fan connector, J4
- User button, S2
- FPGA JTAG connector, J9
- 4bit DIP switch, S1
- I²C header for LTM4676A DC-DC converter, J10
- System Controller CPLD JTAG header, J8
- 1x Green LED connected to SC CPLD, D11
- 2-pin 5V FAN header, J6
- System Controller CPLD (Lattice Semiconductor LCMXO2-1200HC), U5
- 6A PowerSoC DC-DC converter @FMC_VADJ (Altera EN5365QI), U7
- 4A PowerSoC DC-DC converter @3.3V (3V3FMC) (Altera EN6347QI), U15
- LDO converter @1.2V (MGTAVTT_FPGA) (TI TPS74401RGW), U17
- LDO converter @1.0V (MGTAVCC_FPGA) (TI TPS74401RGW), U18
- 4A PowerSoC DC-DC converter @1.8V (Altera EN6347QI), U7
Initial Delivery State
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Control Signals
To get started with TEF1001 board, some basic control signals are essential and are described in the following table:
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Signals, Interfaces and Pins
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FMC HPC Connector
I/O signals and interfaces connected to the FPGA SoCs I/O bank and FMC connector J2:
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For detailed information about the pin out, please refer to the Pin-out Tables.
FMC connector J2 MGT Lanes:
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FMC connector J2 reference clock sources:
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FMC connector J2 VCC/VCCIO:
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FMC connector J2 Cooling Fan:
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PCI Express Interface
The TEF1001 FPGA board is a PCI Express card designed to fit into systems with PCI Express x8 slots and has a data transmission capability which meets PCIe Gen. 2 with 4 GTX lanes routed to the PCIe interface.
Following table lists lane number, MGT bank number, transceiver type, signal schematic name, connector and FPGA pins connection:
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JTAG Connectors
There are two JTAG connectors J8 and J9 available on the TEF1001 board:
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FAN Connectors
The TEF1001 board offers one FAN connector for cooling the FPGA device and one built-in FAN for the FMC modules.
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On-board Peripherals
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System Controller CPLD
The System Controller CPLD (U5) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.
For detailed function of the pins and signals, the internal signal assignment and the implemented logic, look to the Wiki reference page of the board's SC CPLD or into its bitstream file.. Table below lists the SC CPLD I/O pins with their default configuration:
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DDR3 SDRAM ECC SO-DIMM Socket
The TEF1001 board supports additional DDR3 ECC SO-DIMM via 204-pin socket U2. The DDR3 memory interface has a 64bit wide databus and is routed to the FPGA banks 32, 33 and 34.
The reference clock signal for the DDR3 interface is generated by the 200.0000MHz MEMS oscillator U1 and is applied to the FPGA bank 33.
There is also a I2C interface between the System Controller CPLD U5 and the DDR3 ECC SO-DIMM memory socket U2.
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It is important to use SO-DIMMs which provide ECC functionality. SO-DIMMs without ECC are not compatible with this board. |
Quad SPI Flash Memory
A 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron N25Q256A, U12) is provided for FPGA configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency. The memory can be accessed indirectly by the FPGA JTAG port (J9) by implementing the functional logic for this purpose inside the FPGA.
Quad SPI Flash memory interface is connected to the FPGA bank 14, QSPI clock is provided by FPGA config bank 0.
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SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
Programmable Clock Generator
There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U13) to generate various reference clocks for the module.
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Oscillators
The FPGA module has following reference clocking sources provided by on-board oscillators and FMC connector J2:
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On-board LEDs
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Configuration DIP-switch
There is one 4-bit DIP-witches S1 present on the TEB0911 board to configure options and set parameters. The following section describes the functionalities of the particular switches.
Table below describes the functionalities of the switches of DIP-switches S3 and S4 at their each positions:
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Push Buttons
There is one push buttons available to the user connected to the SC CPLD U5:
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Power and Power-On Sequence
Power Consumption
The maximum power consumption of a module mainly depends on the design running on the FPGA.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
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* TBD - To Be Determined soon with reference design setup.
It is recommended to connect the ATX connector J5 to a 12V power supply source with minimum current capability of 6A to provide a sufficient power source to the board. Only one power source is needed at the same time, the system disconnects automatically PCIe power supply from PCIe edge connector J1 if the board is powered by the ATX connector J5.
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To avoid any damage to the module, check for stabilized on-board voltages should be carried out (i.e. power good and enable signals) before powering up any FPGA's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
Power Distribution Dependencies
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Power-On Sequence
The TEF1001 board meets the recommended criteria to power up the Xilinx FPGA properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the FPGA chip and powering up the on-board voltages.
Some of the voltages are handled by the System Controller CPLD using "Power good"-signals from the voltage regulators:
Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:
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Bank Voltages
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Power Rails
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Technical Specifications
Absolute Maximum Ratings
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Assembly variants for higher storage temperature range are available on request. |
Recommended Operating Conditions
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Block Diagram
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Main Components
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- Xilinx Kintex XC7K-2FBG676I FPGA SoC, U6
- ANSI/VITA 57.1 compliant FMC HPC connector, J2
- Cooling fan 5VDC M1 (45X5MM, 0.7W, 1.06CFM), M1
- PCIe x8 connector, J1
- SO-DIMM socket, U2
- 6-pin 12V power connector, J5
- Step-down DC-DC converter @1.5V and @4V (LT LTM4676A), U3
- Step-down DC-DC converter @1.0V (LT LTM4676A), U4
- 256 Mbit Quad SPI Flash Memory (Micron N25Q256A), U12
- 10x Green user LEDs connected to FPGA, D1 ... D10
- 4-wire PWM fan connector, J4
- User button, S2
- FPGA JTAG connector, J9
- 4bit DIP switch, S1
- I²C header for LTM4676A DC-DC converter, J10
- System Controller CPLD JTAG header, J8
- 1x Green LED connected to SC CPLD, D11
- 2-pin 5V FAN header, J6
- System Controller CPLD (Lattice Semiconductor LCMXO2-1200HC), U5
- 6A PowerSoC DC-DC converter @FMC_VADJ (Altera EN5365QI), U7
- 4A PowerSoC DC-DC converter @3.3V (3V3FMC) (Altera EN6347QI), U15
- LDO converter @1.2V (MGTAVTT_FPGA) (TI TPS74401RGW), U17
- LDO converter @1.0V (MGTAVCC_FPGA) (TI TPS74401RGW), U18
- 4A PowerSoC DC-DC converter @1.8V (Altera EN6347QI), U7
Initial Delivery State
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SPI Flash OTP Area
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Empty, not programmed
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Except serial number programmed by flash vendor
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SPI Flash Quad Enable bit
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Programmed
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SPI Flash main array
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demo design
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eFUSE USER
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Not programmed
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-
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eFUSE Security
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Not programmed
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Table 1: Initial delivery state of programmable devices on the module
Boot Process
By default the configuration mode pins M[2:0] of the FPGA are set to QSPI mode (Master SPI), hence the FPGA is configured from serial NOR flash at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the QSPI flash memory.
Signals, Interfaces and Pins
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FMC HPC Connector I/Os
I/O signals connected to the SoCs I/O bank and FMC connector J2:
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For detailed information about the pin out, please refer to the Pin-out Tables.
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PCI Express Interface
The TEF1001 FPGA board is a PCI Express card designed to fit into systems with PCI Express x8 slots (PCIe 2.0 or higher) and is PCIe Gen. 2 capable. See next section for the overview of FPGA MGT lanes routed to the PCIe interface.
MGT Lanes
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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. The MGT lanes are connected to the FMC connector and to the PCIe x8 connector. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, connector and FPGA pins connection:
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- PER3_P
- PER3_N
- PET3_P
- PET3_N
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- J1-A29
- J1-A30
- J1-B27
- J1-B28
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- MGTXTXP0_115, P2
- MGTXTXN0_115, P1
- MGTXRXP0_115, R4
- MGTXRXN0_115, R3
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- PER2_P
- PER2_N
- PET2_P
- PET2_N
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- J1-A25
- J1-A26
- J1-B23
- J1-B24
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- MGTXTXP1_115, M2
- MGTXTXN1_115, M1
- MGTXRXP1_115, N4
- MGTXRXN1_115, N3
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- PER1_P
- PER1_N
- PET1_P
- PET1_N
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- J1-A21
- J1-A22
- J1-B19
- J1-B20
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- MGTXTXP2_115, K2
- MGTXTXN2_115, K1
- MGTXRXP2_115, L4
- MGTXRXN2_115, L3
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- PER0_P
- PER0_N
- PET0_P
- PET0_N
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- J1-A16
- J1-A17
- J1-B14
- J1-B15
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- MGTXTXP3_115, H2
- MGTXTXN3_115, H1
- MGTXRXP3_115, J4
- MGTXRXN3_115, J3
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- DP3_M2C_P
- DP3_M2C_N
- DP3_C2M_P
- DP3_C2M_N
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- J2-A10
- J2-A11
- J2-A30
- J2-A31
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- MGTXRXP0_116, G4
- MGTXRXN0_116, G3
- MGTXTXP0_116, F2
- MGTXTXN0_116, F1
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- DP2_M2C_P
- DP2_M2C_N
- DP2_C2M_P
- DP2_C2M_N
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- J2-A6
- J2-A7
- J2-A26
- J2-A27
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- MGTXRXP1_116, E4
- MGTXRXN1_116, E3
- MGTXTXP1_116, D2
- MGTXTXN1_116, D1
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- DP1_M2C_P
- DP1_M2C_N
- DP1_C2M_P
- DP1_C2M_N
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- J2-A2
- J2-A3
- J2-A22
- J2-A23
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- MGTXRXP2_116, C4
- MGTXRXN2_116, C3
- MGTXTXP2_116, B2
- MGTXTXN2_116, B1
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- DP0_M2C_P
- DP0_M2C_N
- DP0_C2M_P
- DP0_C2M_N
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- J2-C6
- J2-C7
- J2-C2
- J2-C3
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- MGTXRXP3_116, B6
- MGTXRXN3_116, B5
- MGTXTXP3_116, A4
- MGTXTXN3_116, A3
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Below are listed MGT banks reference clock sources:
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Table 4: MGT reference clock sources
JTAG Interface
There are three JTAG interfaces available on the TEF1001 board:
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CPLD JTAG
VCCIO: 3.3V
Connector: J8
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J8-4
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FPGA JTAG
VCCIO: 1.8V
Connector: J9
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FMC JTAG
VCCIO: 3.3V
Connector: J2
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Table 5: JTAG interface signals
System Controller CPLD I/O Pins
Special purpose pins are connected to the System Controller CPLD and have following default configuration:
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JTAG signals between
SC CPLD and FPGA
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Program FPGA or SC CPLD depending on pin JTAGMODE.
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PL I/O's are 3-stated until configuration of the FPGA completes.
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Low active FPGA initialization pin or configuration error signal.
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Table 6: System Controller CPLD I/O pins
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- FPGA_IIC_SDA, pin 24
- FPGA_IIC_SCL, pin 25
- FPGA_IIC_OE, pin 19
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- FPGA bank 16, pin V29
- FPGA bank 16, pin W29
- FPGA bank 16, pin W26
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VCCIO: 1V8, all with pull-up to 1V8.
Following devices and connectors are linked to the FPGA_IIC I2C interface:
- DC-DC converter U3 and U4 (LT LTM4676)
- Programmable quad clock generator U13
- FMC connector J2
- PCIe connector J1
Note: FPGA_IIC_OE must kept high for I2C operation.
For I2C slave device addresses refer to the component datasheets.
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User I/Os
External LVDS pairs
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10 I/Os
5 x LVDS pairs
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- EX0_P ... EX4_P
- EX0_N ... EX4_N
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- IDC header J7
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Can also be used for single-ended signaling.
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User I/Os
Internal LVDS pairs
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13 I/Os
6 x LVDS pairs
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- FEX0_P ... FEX5_P
- FEX0_N ... FEX5_N
- FEX_DIR (single-ended I/O)
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- FPGA bank 18
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VCCIO: 1V8
Can also be used for single-ended signaling.
FPGA bank 18 has also reference clock input from FMC connector (CLK2, CLK3) and clock synthesizer U9 (FCLK).
Internal signal assignment:
FEX_DIR <= FMC_PRSNT_M2C_L
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- DONE, pin 7
- PROGRAM_B, pin 8
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- FPGA bank 0, pin V8
- FPGA bank 0, pin U8
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- PLL_SCL, pin 14
- PLL_SDA, pin 15
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- U13, pin 12
- U13, pin 19
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VCCIO: 1V8
Only PLL_SDA has 1V8 pull-up.
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- F1SENSE, pin 99
- F1PWM, pin 98
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- J4-3 (active low)
- J4-4
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Internal signal assignment:
- FEX_5_P <= F1SENSE
- FEX_5_N => F1PWM
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- BUTTON, pin 77
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- Switch S2
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- LED1, pin 76
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- LED D1 (green)
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Fast blinking, when FPGA is not programmed.
Internal signal assignment:
- LED1 <= Button S2 or FEX0_P
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PCIe control line RESET_B
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- PCIE_RSTB, pin 37
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- J1-A11
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Internal signal assignment:
- FEX_4_N <= PCIE_RSTB
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Control interface to clock synthesizer U9 (TI LMK04828B)
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SPI (3 I/Os),
4 I/Os
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- CLK_SYNTH_SDIO, pin 75
- CLK_SYNTH_SCK, pin 74
- CLK_SYNTH_RESET, pin 54
- CLK_SYNTH_CS, pin 53
- CLK_SYNTH_SYNC, pin 52
- LMK_STAT0, pin 62
- LMK_STAT1, pin 63
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- U9, pin 20
- U9, pin 19
- U9, pin 5
- U9, pin 18
- U9, pin 6
- U9, pin 31
- U9, pin 48
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Pull up to 3V3PCI.
- Internal signal assignment:
- LMK_SCK <= FEX_1_P
- LMK_SDIO <= FEX_1_N
- LMK_CS <= FEX_3_P
- LMK_SYNC <= EX_3_N
- LMK_RESET <= FEX_4_P
- FEX_2_P => LMK_SDIO (FEX_2_N must be 0)
- LMK_STAT0 and LMK_STAT1 signals are not used.
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I2C (2 I/Os),
2 I/Os
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- LTM_SCL, pin 67
- LTM_SDA, pin 66
- LTM1_ALERT, pin 65
- LTM2_ALERT, pin 64
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- U4, pin E6 and U3, pin E6
- U4, pin D6 and U3, pin D6
- U4, pin E5
- U3, pin E5
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3V3 pull-ups.
LTM I2C interface is also accessible trough header J10.
LTM1_ALERT and LTM2_ALERT signals are not used.
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- EN_1V8, pin 58
- PG_1V8, pin 59
- EN_FMC_VADJ, pin 60
- PG_FMC_VADJ, pin 61
- EN_3V3, pin 51
- PG_3V3, pin 57
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- U20, pin 27
- U20, pin 28
- U7, pin 27
- U7, pin 28
- U15, pin 27
- U15, pin 28
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Sequence of the supply voltages depend on the System Controller CPLD firmware.
EN_1V8, EN_3V3 and EN_FMC_VADJ will be set simultaneously at start-up.
PG signals will not be evaluated.
For detailed function of the pins and signals, the internal signal assignment and the implemented logic, look to the Wiki reference page of the module's SC CPLD or into its bitstream file.
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Quad SPI Interface
Quad SPI interface is connected to the FPGA configuration bank 0.
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Table 7: Quad SPI interface signals and connections
I2C Interface
On-module I²C interface is routed from PL bank 65 I/O pins (PLL_SCL and PLL_SDA) to the I²C interface of Si5338 PLL quad clock generator U2, also two further pins of bank 65 can be used as external I²C interface of the modue:
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'PLL_SCL', pin AB20
'PLL_SDA' pin AB19
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Si5338 U2, pin 12
Si5338 U2, pin 19
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'B65_SCL', pin Y19
'B65_SDA', pin AA19
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B2B JM1, pin 95
B2B JM1, pin 93
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Table 8: I2C slave device addresses
On-board Peripherals
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System Controller CPLD
The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.
For detailed information, refer to the reference page of the SC CPLD firmware of this module.
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DDR3 SD-RAM SODIMM Socket
By default TE0841 module has two K4A8G165WB-BIRC DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 2 GBytes of on-module RAM. Different memory sizes are available optionally.
Quad SPI Flash Memory
On-module QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q512A11G1240E with 512-Mbit (64 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
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SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
Programmable Clock Generator
There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.
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IN1
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-
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not used
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IN3
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Reference input clock
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IN4
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IN5
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CLK0A
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CLK1_P
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FPGA bank 45, default 100MHz*
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FPGA MGT bank 225 reference clock, default 125MHz*
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CLK0_P
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FPGA bank 45, default 156,25MHz*
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Table 9: Programmable quad PLL clock generator inputs and outputs, *PCB REV01 is not programmed
Oscillators
The FPGA module has following reference clocking signals provided by external baseboard sources and on-board oscillators:
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Enable by FPGA bank 65, pin AF24
Signal: 'ENOSC'
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Table 10: Reference clock signals
On-board LEDs
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Table 11: On-board LEDs
Power and Power-On Sequence
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Power Consumption
The maximum power consumption of a module mainly depends on the design running on the FPGA.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
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Table 12: Typical power consumption
* TBD - To Be Determined soon with reference design setup.
Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.
For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.
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To avoid any damage to the module, check for stabilized on-board voltages should be carried out (i.e. power good and enable signals) before powering up any FPGA's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
Power Distribution Dependencies
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title | Figure 3: TE0841-02 Power Distribution Diagram |
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See also Xilinx datasheet DS892 for additional information. User should also check related base board documentation when intending base board design for TE0841 module.
Power-On Sequence
The TE0841 SoM meets the recommended criteria to power up the Xilinx FPGA properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the FPGA chip and powering up the on-board voltages.
Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:
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title | Figure 4: TE0841-02 Power-On Sequence Diagram |
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Power Rails
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B2B JM1 Pins
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B2B JM2 Pins
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Input/Output
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VBAT_IN
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Table 13: Module power rails
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Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered). |
Bank Voltages
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Bank
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Voltage
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Voltage Range
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PL_1.8V
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1.8V
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Table 14: Module PL I/O bank voltages
Variants Currently In Production
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Technical Specifications
Absolute Maximum Ratings
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Parameter
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Units
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Reference Document
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VIN supply voltage
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GTH and GTY transceiver receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage
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1.260
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Storage temperature
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-40
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+100
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1) Temperature range may vary depending on assembly options
2) The operating temperature range of the FPGA soC and on-board peripherals are junction and also ambient operating temperature ranges
Board operating temperature range depends also on customer design and cooling solution. Please contact us for options.
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Please check also Xilinx datasheet DS182 for complete list of absolute maximum and recommended operating ratings. |
Physical Dimensions
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Revision History
Hardware Revision History
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Table 16: Module absolute maximum ratings
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Recommended Operating Conditions
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3.400
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Supply voltage for HP I/O banks (VCCO)
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0.950
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1.890
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I/O input voltage for HR I/O banks
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–0.200
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Industrial Module Operating Temperature Range
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Table 17: Module recommended operating conditions
Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
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Please check also Xilinx datasheet DS892 for complete list of absolute maximum and recommended operating ratings. |
Physical Dimensions
Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: 1.65 mm.
Highest part on PCB: approximately 3 mm. Please download the step model for exact numbers.
All dimensions are given in millimeters.
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Revision History
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Document Change History
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