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The SoC module has following reference clocking signals provided by external baseboard sources and on-board oscillators:
| Clock source | Schematic name | Frequency | Clock input destination |
|---|---|---|---|
| B2B connector J3, pins J3-74/J3-76 | CLKIN_N, CLKIN_P | User | Quad PLL clock generator U16, pin 1/2 |
| B2B connector J3, pins J3-75/J3-77 | MGT_CLK0_P, MGT_CLK0_N | User | MGT bank 112, pin R6/R5 |
| B2B connector J3, pins J3-81/J3-83 | MGT_CLK2_P, MGT_CLK2_N | User | MGT bank 111, pin W6/W5 |
| SiTime SiT8008BI oscillator, U21 | - | 25.000000 MHz | Quad PLL clock generator U16, pin 3 |
SiTime SiT8008BI oscillator, U12 | PS_CLK | 33.333333 MHz | Bank 500 (MIO0 bank), pin B24 |
| SiTime SiT8008BI oscillator, U23 | OTG-RCLK | 52.000000 MHz | USB 2.0 transceiver PHY U32, pin 26 |
| SiTime SiT8008BI oscillator, U9 | ETH_CLKIN | 25.000000 MHz | Gigabit Ethernet PHY U7, pin 34 |
Table 7: Clock sources overview
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| PHY Pin | ZYNQ PS | B2B | Notes |
|---|---|---|---|
| MDC/MDIO | MIO52, MIO53 | - | - |
| PHY LEDs | - | PHY_LED0: J2-144 | - |
| PHY_LED2 / INTn: | - | J2-148 | Active low interrupt line |
| PHY_CLK125M | - | J2-150 | 125 MHz Ethernet PHY clock out |
| CONFIG | - | - | Permanent high (PS_1.8V) |
| RESETn | MIO9 | - | Active low reset line |
| RGMII | MIO16..MIO27 | - | Reduced Gigabit Media Independent Interface |
| SGMII | - | - | Serial Gigabit Media Independent Interface |
| MDI | - | PHY_MDI0: J2-120 / J2-122 PHY_MDI1: J2-126 / J2-128 PHY_MDI2: J2-132 / J2-134 PHY_MDI3: J2-138 / J2-140 | Media Independent Dependent Interface |
Table 9: Ethernet PHY interface connections
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USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 25.000000 MHz oscillator (U15).
| PHY Pin | ZYNQ Pin | B2B Name | Notes |
|---|---|---|---|
| ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY. |
| REFCLK | - | - | 52MHz from on board oscillator (U33). |
| REFSEL[0..2] | - | - | All pins set to GND selects the external reference clock frequency (52.000000 MHz). |
| RESETB | MIO7 | - | Active-low reset line. |
| CLKOUT | MIO36 | - | Set to high (1.8V VDDIO level) to select reference clock operation mode. |
| DP, DM | - | OTG_D_P, OTG_D_N, pin J2-149 / J2-151 | USB data lines. |
| CPEN | - | VBUS_V_EN, pin J2-141 | External USB power switch active-high enable signal. |
| VBUS | - | USB_VBUS, pin J2-145 | Connect to USB VBUS via a series of resistors, see reference schematics. |
| ID | - | OTG_ID, pin J2-143 | For an A-device connect to the ground. For a B-device ,leave floating. |
Table 10: USB PHY interface connections
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Bank | Schematic Name | Voltage | Voltage Range |
|---|---|---|---|
| 0 (config) | VCCIO_0 | PL_1.8V if R67 is equipped | - |
| 500 (MIO0) | PS_1.8V | 1.8V | - |
| 501 (MIO1) | PS_1.8V | 1.8V | - |
| 502 (DDR3) | 1.35V | 1.35V | - |
| 12 HR | VCCIO_12 | User | HR: 1.2V to 3.3V |
| 13 HR | VCCIO_13 | User | HR: 1.2V to 3.3V |
| 33 HP | VCCIO_33 | User | HP: 1.2V to 1.8V |
| 34 HP | VCCIO_34 | User | HP: 1.2V to 1.8V |
| 35 HP | VCCIO_35 | User | HP: 1.2V to 1.8V |
Table 16: Range of SoC module's bank voltages
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