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Bank

Type

Lane Count

B2B Connector

Schematics Names / Connector Pins

MGT Bank's Reference Clock Inputs (LVDS pairs)

111

GTX

4

J1

MGT_RX4_P, MGT_RX4_N, pins J1-23, J1-21
MGT_TX4_P, MGT_TX4_N, pins J1-22, J1-20

MGT_RX5_P, MGT_RX5_N, pins J1-17, J1-15
MGT_TX5_P, MGT_TX5_N, pins J1-16, J1-14

MGT_RX6_P, MGT_RX6_N, pins J1-11, J1-9
MGT_TX6_P, MGT_TX6_N, pins J1-10, J1-8

MGT_RX7_P, MGT_RX7_N, pins J1-3, J1-5
MGT_TX7_P, MGT_TX7_N, pins J1-4, J1-6

1 Reference clock MGT_CLK3 from programmable
quad clock generator U16 to bank's pins AA6/AA5.

1 Reference clock MGT_CLK2 from B2B connector J3
(pins J3 pins 81 and83 -81, J3-83) to bank's pins W6/W5.

112

GTX

4

J3

MGT_RX3_P, MGT_RX3_N, pins J3-68, J3-70
MGT_TX3_P, MGT_TX3_N, pins J3-69, J3-71

MGT_RX2_P, MGT_RX2_N, pins J3-62, J3-64
MGT_TX2_P, MGT_TX2_N, pins J3-63, J3-65

MGT_RX1_P, MGT_RX1_N, pins J3-56, J3-58
MGT_TX1_P, MGT_TX1_N, pins J3-57, J3-59

MGT_RX0_P, MGT_RX0_N, pins J3-50, J3-52
MGT_TX0_P, MGT_TX0_N, pins J3-51, J3-53

1 Reference clock MGT_CLK1 from programmable
quad clock generator U16 to bank's pins U6/U5.

1 Reference clock MGT_CLK0 from B2B connector J3
(pins J3 pins -75 and , J3-77) to bank's pins R6/R5.

Table 3: SoC's MGT lanes connections to the B2B connectors

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Pin Name	Mode	Function	B2B Connector Pin	Default Configuration
JTAG_EN	Input	JTAG select	J1-148	During normal operating mode the JTAG_EN pin should be in the low state and JTAG signals are forwarded to the Zynq SoC. If JTAG_EN pin is set to high or left open the JTAG signals are forwarded to the System Controller CPLD.
RST_IN_N	Input	Reset	J2-131	Low-active Power-On reset pin, controls POR_B-signal (bank 500, pin C23) of Zynq chip.
PS_SRST	Input	Reset	J2-152	Low-active PS system-reset pin of Zynq chip.
BOOTMODE	Output	Boot mode	J2-133	Control line which sets in conjunction with signal 'BOOTMODE1' (B2B-pin J2-133) the boot source of the Zynq chip. See section "Boot Modes". Permanent logic high in standard SC-CPLD firmware.
PWR_PL_OK	Input	Power good	J2-135	Indicates stable state of PL supply voltage (low-active) after power-up sequence.
PWR_PS_OK	Input	Power good	J2-139	Indicates stable state of PS supply voltage (low-active) after power-up sequence.
EN_PL	Output	Enable signal	-	Low active Enable-signal for activating PL supply voltage. Permanent logic high in standard SC-CPLD firmware.
MIO8	Input	PS MIO	-	User I/O (pulled-up to PS_1.8V)
MIO0	Input	PS MIO	J2-137	User I/O
RTC_INT	Input	Interrupt signal	-	Interrupt-signal from on-board RTC.
LED	Output	LED control	-	Green LED D1, indicates SC-CPLD activity by blinking.

Table 5: System Controller CPLD special purpose I/O pins

On-board LEDs

Default MIO Mapping

The configuration of the I/O's MIO12 - MIO15 and MIO40 - MIO51 are depending on the base-board peripherals connected to these pins.

D1

MIO

Function

LED

Color

Connected to

Description and Notes

Green

System Controller CPLD, bank 3, pin 5

System main status LED, blinking indicates system activity

D2

Red

Zynq chip (U1), bank 0 (config bank), 'DONE' (pin W9)

Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured.

This LED remains OFF if System Controller CPLD can not power up the PL supply voltage.

Table 6: LEDs of the module

Clocking

The SoC module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

...

CLKIN_N, CLKIN_P

...

MGT_CLK0_P, MGT_CLK0_N

...

SiTime SiT8008BI oscillator, U12

...

MIO	Function	Connected to	Notes
0	GPIO	J2-137, SC CPLD bank 2, pin 14	User configurable I/O on B2B.	16..27	ETH0	Ethernet PHY U7	RGMII
1	QSPI0	QSPI Flash Memory U14, pin C2	SPI Flash-CS	28..39	USB0	USB PHY U32	ULPI
2	QSPI0	QSPI Flash Memory U14, pin D3	SPI Flash-DQ0	40	-	J2-150	User configurable I/O on B2B.
3	QSPI0	QSPI Flash Memory U14, pin D2	SPI Flash-DQ1	41	-	J2-152	User configurable I/O on B2B.
4	QSPI0	QSPI Flash Memory U14, pin C4	SPI Flash-DQ2	42	-	J2-154	User configurable I/O on B2B.
5	QSPI0	QSPI Flash Memory U14, pin D4	SPI Flash-DQ3	43	-	J2-156	User configurable I/O on B2B.
6	QSPI0	QSPI Flash Memory U14, pin B2	SPI Flash-SCK	44	-	J2-158	User configurable I/O on B2B.
7	GPIO	USB PHY U32, pin 27	Low active USB PHY Reset (pulled-up to PS_1.8V)	45	-	J2-160	User configurable I/O on B2B.
8	GPIO	SC CPLD bank 2, pin 13	User I/O (pulled-up to PS_1.8V)	46	-	J2-145

Table 7: Clock sources overview

Default MIO Mapping

The configuration of the I/O's MIO12 - MIO15 and MIO40 - MIO51 are depending on the base-board peripherals connected to these pins.

J2-137, SC CPLD bank 2, pin 14ETH015667GPIO 278

MIO	Function	Connected to	Notes		MIO	Function	Connected to	Notes
0	GPIO		User configurable I/O on B2B.		16..27
9	GPIO	Ethernet PHY U7	RGMII
1	QSPI0	QSPI Flash Memory U14, pin C2	SPI Flash-CS		28..39	USB0	USB PHY U32	ULPI
, pin 16	Ethernet PHY Reset		47	-	J2-147	User configurable I/O on B2B.
10	I²C	SCL line I²C-interface	1.8V ref. voltage		48	2	QSPI0	QSPI Flash Memory U14, pin D3	SPI Flash-DQ0		40	-	J2-150149	User configurable I/O on B2B.
311	QSPI0	QSPI Flash Memory U14, pin D2	I²C	SDA line I²C-interface	1.8V ref. voltageSPI Flash-DQ1		4149	-	J2-152151	User configurable I/O on B2B.
412	QSPI0	QSPI Flash Memory U14, pin C4	-	J2-123	User configurable I/O on B2B.SPI Flash-DQ2		4250	-	J2-154153	User configurable I/O on B2B.	5	QSPI0	QSPI Flash Memory U14, pin D4	SPI Flash-DQ3		43
13	-	J2-	125	User configurable I/O on B2B.		QSPI0	QSPI Flash Memory U14, pin B2	SPI Flash-SCK		51	-	J2-155	User configurable I/O on B2B.
1444	-	J2-158127	User configurable I/O on B2B.		52	ETH0	USB PHY U32, pin	7	MDC
15	Low active USB PHY Reset (pulled-up to PS_1.8V)		45	-	J2-160129	User configurable I/O on B2B.		53	GPIO	SC CPLD bank 2, pin 13	User I/O (pulled-up to PS_1.8V)		46	-	J2-145	User configurable I/O on B2B.
9	GPIO	Ethernet PHY U7, pin 16	Ethernet PHY Reset		47	-	J2-147	User configurable I/O on B2B.
10	I²C	SCL line I²C-interface	1.8V ref. voltage		48	-	J2-149	User configurable I/O on B2B.
11	I²C	SDA line I²C-interface	1.8V ref. voltage		49	-	J2-151	User configurable I/O on B2B.
12	-	J2-123	User configurable I/O on B2B.		50	-	J2-153	User configurable I/O on B2B.
13	-	J2-125	User configurable I/O on B2B.		51	-	J2-155	User configurable I/O on B2B.
14	-	J2-127	User configurable I/O on B2B.		52	ETH0	USB PHY U32, pin 7	MDC
15	-	J2-129	User configurable I/O on B2B.		53	ETH0	USB PHY U32, pin 8	MDIO

Table 8: Default MIO Mapping

Gigabit Ethernet Interface

ETH0

USB PHY U32, pin 8

MDIO

Table 6: Default MIO Mapping

Gigabit Ethernet Interface

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U9). The 125MHz PHY output clock (PHY_CLK125M) is routed to the B2B connector J2 pin 150.

PHY Pin	ZYNQ PS	B2B	Notes
MDC/MDIO	MIO52, MIO53	-	-
PHY LEDs	-	PHY_LED0: J2-144 PHY_LED1: J2-146	-
PHY_LED2 / INTn:	-	J2-148	Active low interrupt line
PHY_CLK125M	-	J2-150	125 MHz Ethernet PHY clock out
CONFIG	-	-	Permanent high (PS_1.8V)
RESETn	MIO9	-	Active low reset line
RGMII	MIO16..MIO27	-	Reduced Gigabit Media Independent Interface
SGMII	-	-	Serial Gigabit Media Independent Interface
MDI	-	PHY_MDI0: J2-120 / J2-122 PHY_MDI1: J2-126 / J2-128 PHY_MDI2: J2-132 / J2-134 PHY_MDI3: J2-138 / J2-140	Media Dependent Interface

Table 7: Ethernet PHY interface connections

USB Interface

USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. The and PHY reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U9U15). The 125MHz PHY output clock (PHY_CLK125M) is routed to the B2B connector J2 pin 150.

MIO52, MIO53

PHY Pin	ZYNQ PSPin	B2B Name	Notes	MDC/MDIO
ULPI	MIO28..39	-	Zynq USB0 MIO pins are connected to the PHY.
REFCLK	-	PHY LEDs	-	PHY_LED0: J2-144 PHY_LED1: J2-146	-
PHY_LED2 / INTn:	-	J2-148	Active low interrupt line
PHY_CLK125M	-	J2-150	125 MHz Ethernet PHY clock out
CONFIG	-	-	Permanent high (PS_1.8V)
RESETn	MIO9	-	Active low reset line
RGMII	MIO16..MIO27	-	Reduced Gigabit Media Independent Interface
SGMII	-	-	Serial Gigabit Media Independent Interface
MDI	-	PHY_MDI0: J2-120 / J2-122 PHY_MDI1: J2-126 / J2-128 PHY_MDI2: J2-132 / J2-134 PHY_MDI3: J2-138 / J2-140	Media Dependent Interface

Table 9: Ethernet PHY interface connections

USB Interface

USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 25.000000 MHz oscillator (U15).

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Table 10: USB PHY interface connections

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

The I²C interface on the B2B connector J2 pins 119 (I2C_33_SCL) and 121 (I2C_33_SDA) have PS_3.3V as a reference voltage.

Except the RTC (U24), all remaining I²C slave devices are operating with the reference voltage PS_1.8V via voltage level translating (3.3V ↔ 1.8V) I²C bus repeater (U17).

I2C addresses for on-board devices are listed in the table below:

...

Table 11: Module's I²C-interfaces overview

Boot Process

TE0745 module supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21.

The current boot mode will be set by the MIO pins MIO3...MIO5. The control line 'BOOTMODE' is connected to the 'MIO4' pin, 'BOOTMODE_1' to 'MIO5'.

Following table describes how to set the control lines to configure the desired boot mode:

...

MIO3

...

JTAG

...

Table 12: Selectable boot modes

On-board Peripherals

Flash

...

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

RTC - Real Time Clock

An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I²C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at ^I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD bank 3 pin 4.

Programmable PLL Clock (Phase-Locked Loop)

There is a Silicon Labs I²C programmable quad PLL clock generator Si5338A (U16) on-board. It's output frequencies can be programmed by using the I²C-bus with address 0x70.

A 25 MHz (U21) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.

Once running, the frequency and other parameters can be changed by programming the device using the I²C-bus connected between the Zynq module (master) and reference clock signal generator (slave).

...

IN1/IN2

...

CLKIN_P, CLKIN_N

...

Reference clock signal from B2B connector J3, pin J3-74/J3-76

(base board decoupling capacitors and termination resistor necessary)

...

IN3

...

reference clock signal from oscillator SiTime SiT8008BI (U21)

...

IN4/IN6

...

IN5

...

not connected

...

CLK0 A/B

...

MGTCLK1_P, MGTCLK1_N

...

reference clock signal to MGT bank 112, pin U6/U5

(100 nF decoupling capacitors)

...

CLK1 A/B

...

clock signal routed to B2B connector, pin J3-80/J3-82

...

CLK2 A/B

...

clock signal routed to B2B connector, pin J3-86/J3-88

...

MGTCLK3_P, MGTCLK3_N

...

reference clock signal to MGT bank 111, pin AA6/AA5

(100 nF decoupling capacitors)

-	52MHz from on board oscillator (U33).
REFSEL[0..2]	-	-	All pins set to GND selects the external reference clock frequency (52.000000 MHz).
RESETB	MIO7	-	Active-low reset line.
CLKOUT	MIO36	-	Set to high (1.8V VDDIO level) to select reference clock operation mode.
DP, DM	-	OTG_D_P, OTG_D_N, pin J2-149 / J2-151	USB data lines.
CPEN	-	VBUS_V_EN, pin J2-141	External USB power switch active-high enable signal.
VBUS	-	USB_VBUS, pin J2-145	Connect to USB VBUS via a series of resistors, see reference schematics.
ID	-	OTG_ID, pin J2-143	For an A-device connect to the ground. For a B-device, leave floating.

Table 8: USB PHY interface connections

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

The I²C interface on the B2B connector J2 pins 119 (I2C_33_SCL) and 121 (I2C_33_SDA) have PS_3.3V as a reference voltage.

Except the RTC (U24), all remaining I²C slave devices are operating with the reference voltage PS_1.8V via voltage level translating (3.3V ↔ 1.8V) I²C bus repeater (U17).

I2C addresses for on-board devices are listed in the table below:

I2C Device	I2C Address	Notes
Zynq chip U1, bank 500 (PS MIO), pins MIO10 (SCL), MIO11 (SDA)	User programmable	Configured as I²C by default
Quad programmable PLL clock generator U16: pins 12 (SCL), 19 (SDA)	0x70	-
MAC Address EEPROM U23, pins 1 (SCL), 3 (SDA)	0x53	-
SC CPLD U2, bank 2, pins 16 (SDA), 17 (SCL)	User programmable	-
RTC, U24	0x6F	-
RTC RAM, U24	0x57	-

Table 9: Module's I²C-interfaces overview

Boot Process

TE0745 module supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21.

The current boot mode will be set by the MIO pins MIO3...MIO5. The control line 'BOOTMODE' is connected to the 'MIO4' pin, 'BOOTMODE_1' to 'MIO5'.

Following table describes how to set the control lines to configure the desired boot mode:

Boot Mode	MIO5 (BOOTMODE_1)	MIO4 (BOOTMODE)	MIO3	Note
JTAG	0	0	0	-
NOR	0	0	1	MIO3 pin is shared with QSPI Flash Memory (QSPI-DQ1)
NAND	0	1	0	-
QSPI Flash Memory	1	0	0	standard mode in current configuration
SD-Card	1	1	0	SD-Card on base board necessary

Table 10: Selectable boot modes

On-board Peripherals

Flash

The TE0745 SoM is equipped with 32 MByte Flash memory for configuration and operation.

Name	IC	ID	PS7	MIO	Notes
SPI Flash	S25FL256SAGBHI20	U14	QSPI0	MIO1..MIO6	-

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

RTC - Real Time Clock

An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I²C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at ^I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD bank 3 pin 4.

Programmable PLL Clock (Phase-Locked Loop)

There is a Silicon Labs I²C programmable quad PLL clock generator Si5338A (U16) on-board. It's output frequencies can be programmed by using the I²C-bus with address 0x70.

A 25 MHz (U21) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.

Once running, the frequency and other parameters can be changed by programming the device using the I²C-bus connected between the Zynq module (master) and reference clock signal generator (slave).

Si5338A (U13) Input	Signal Schematic Name	Note
IN1/IN2	CLKIN_P, CLKIN_N	Reference clock signal from B2B connector J3, pin J3-74/J3-76 (base board decoupling capacitors and termination resistor necessary).
IN3	reference clock signal from oscillator SiTime SiT8008BI (U21)	25.000000 MHz fixed frequency.
IN4/IN6	pins put to GND	LSB (pin 'IN4') of the default I²C-adress 0x70 not activated.
IN5	not connected	-
Si5338A (U13) Output	Signal Schematic Name	Note
CLK0 A/B	MGTCLK1_P, MGTCLK1_N	Reference clock signal to MGT bank 112, pin U6/U5 (100 nF decoupling capacitors).
CLK1 A/B	CLK1_P, CLK1_N	Clock signal routed to B2B connector, pin J3-80/J3-82.
CLK2 A/B	CLK2_P, CLK2_N	Clock signal routed to B2B connector, pin J3-86/J3-88.
CLK3 A/B	MGTCLK3_P, MGTCLK3_N	Reference clock signal to MGT bank 111, pin AA6/AA5 (100 nF decoupling capacitors).

Table 11: Pin description of PLL clock generator Si5338A

Clocking

The SoC module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

Clock Source	Schematic Name	Frequency	Clock Input Destination
SiTime SiT8008BI oscillator, U21	-	25.000000 MHz	Quad PLL clock generator U16, pin 3
SiTime SiT8008BI oscillator, U12	PS_CLK	33.333333 MHz	Bank 500 (MIO0 bank), pin B24
SiTime SiT8008BI oscillator, U23	OTG-RCLK	52.000000 MHz	USB 2.0 transceiver PHY U32, pin 26
SiTime SiT8008BI oscillator, U9	ETH_CLKIN	25.000000 MHz	Gigabit Ethernet PHY U7, pin 34

Table 12: Clock sources overview

On-board LEDs

LED

Color

Connected to

Description and Notes

D1

Green

System Controller CPLD, bank 3, pin 5

System main status LED, blinking indicates system activity

D2

Red

Zynq chip (U1), bank 0 (config bank), 'DONE' (pin W9)

Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured.

This LED remains OFF if System Controller CPLD can not power up the PL supply voltage.

Table 13: LEDs of the moduleTable 13: Pin description of PLL clock generator Si5338A

Power and Power-On Sequence

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Trenz Electronic Documentation

Versions Compared

Old Version 55

New Version 56

Key

On-board LEDs

Default MIO Mapping

Clocking

Default MIO Mapping

Gigabit Ethernet Interface

Gigabit Ethernet Interface

USB Interface

USB Interface

I2C Interface

Boot Process

On-board Peripherals

Flash

MAC Address EEPROM

RTC - Real Time Clock

Programmable PLL Clock (Phase-Locked Loop)

I2C Interface

Boot Process

On-board Peripherals

Flash

MAC Address EEPROM

RTC - Real Time Clock

Programmable PLL Clock (Phase-Locked Loop)

Clocking

On-board LEDs

Power and Power-On Sequence