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The MGT bank signals of the SoC are routed to the B2B connectors J1 and J3. There are 8 high-speed bi-directional data lanes (Xilinx GTX transceivers) available composed as differential signaling pairs for both directions (RX/TX). On B2B connector J3 there are also clock input pins for MGT transceivers.
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| Si5338A (U13) Input | Signal Schematic Name | Note |
|---|---|---|
IN1/IN2 | CLKIN_P, CLKIN_N | Reference clock signal from B2B connector J3, pin pins J3-74/, J3-76 |
IN3 | reference clock signal from oscillator SiTime SiT8008BI (U21) | 25.000000 MHz fixed frequency. |
IN4/IN6 | pins put to GND | LSB (pin 'IN4') of the default I²C-adress 0x70 not activated. |
IN5 | not connected | - |
| Si5338A (U13) Output | Signal Schematic Name | Note |
CLK0 A/B | MGTCLK1_P, MGTCLK1_N | Reference clock signal to MGT bank 112, pin pins U6/U5 |
CLK1 A/B | CLK1_P, CLK1_N | Clock signal routed to B2B connector, pin pins J3-80/, J3-82. |
CLK2 A/B | CLK2_P, CLK2_N | Clock signal routed to B2B connector, pin pins J3-86/, J3-88. |
| CLK3 A/B | MGTCLK3_P, MGTCLK3_N | Reference clock signal to MGT bank 111, pin pins AA6/AA5 |
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The SoC module has following reference clocking signals provided by external baseboard sources and on-board oscillators:
| Clock Source | Schematic Name | Frequency | Clock Input Destination |
|---|---|---|---|
| SiTime SiT8008BI oscillator, U21 | - | 25.000000 MHz | Quad PLL clock generator U16, pin 3 |
SiTime SiT8008BI oscillator, U12 | PS_CLK | 33.333333 MHz | Bank 500 (MIO0 bank), pin B24 |
| SiTime SiT8008BI oscillator, U23 | OTG-RCLK | 52.000000 MHz | USB 2.0 transceiver PHY U32, pin 26 |
| SiTime SiT8008BI oscillator, U9 | ETH_CLKIN | 25.000000 MHz | Gigabit Ethernet PHY U7, pin 34 |
Table 12: Clock sources overview
On-board LEDs
| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
D1 | Green | System Controller CPLD, bank 3, pin 5 | System main status LED, blinking indicates system activity |
D2 | Red | Zynq chip (U1), bank 0 (config bank), 'DONE' (pin W9) | Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured. This LED remains OFF if System Controller CPLD can not power up the PL supply voltage. |
Table 13: LEDs of the module
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