Page History

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1. Xilinx Zynq XC7Z family SoC, U1
2. 256 Mbit Quad SPI Flash memory Micron N25Q256A, U12
3. Reference clock signal oscillator SiTime SiT8008BI @33.333333 MHz, U12
4. Reference clock signal oscillator SiTime SiT8008BI @25.000000 MHz, U9
5. Marvell Alaska 88E1512 Gigabit Ethernet PHY, U3
6. Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16-bit word width), U3
7. TI TPS51206 DDR3 memory termination regulator with buffered reference voltage VTTREF, U18
8. Intersil ISL12020MIRZ Real-Time-Clock, U24
9. TI TCA9517 level-shifting I²C bus repeater, U17
10. Red LED, D2
    
11. Green LED, D1
12. Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 banks a 32 MWords, 16 Bit word width), U5
13. Altera Enpirion EN63A0QI 12A DC-DC PowerSoC @1.0V (VCCINT), U4
    
14. TI TPS74401RGW LDO DC-DC regulator @1.2V (MGTAVTT), U8
15. TI TPS72018DRVR LDO DC-DC regulator @1.8V (MGTAUX), U6
16. TI TPS74401RGW LDO DC-DC regulator @1.0V (MGTAVCC), U11
17. Silicon Labs Si5338A I²C Programmable Quad Clock Generator, U13
18. Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U21
19. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J3
20. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J1
21. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J2
22. 256 Mbit Quad SPI Flash memory (Micron N25Q256A), U14
23. Microchip USB3320 USB transceiver PHY , U32
24. Reference clock signal oscillator SiTime SiT8008BI @52.000000 MHz, U33
25. Microchip 24AA025E48 EEPROM for MAC address, U23
    
26. Lattice Semiconductor MachXO2-256HC System Controller CPLD, U2
    

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The on-board voltages of the TE0745 SoC module will be powered-up in order of a determined sequence after the external voltages 'PL_VIN', 'PS_VIN' and 'PS_3.3V' are available. All those power-rails can be powered up, with 3.3V power sources, also shared.

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It is important that all baseboard I/Os are 3-stated at power-on until the "Power Good"-signals 'PWR_PS_OK' (J2-139) and 'PWR_PL_OK' (J2-135) are high, meaning that all on-module voltages have become stable and module is properly powered up.

Following diagram clarifies the sequence of enabling There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DCDC converters, which power up further DCDC converters and the particular on-board voltages:

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Figure 3: Power -up sequence diagramDistribution Diagram

See Xilinx datasheet data sheet DS191 for additional information. User should also check related base board documentation when intending base board design for TE0745 module.

Power

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-On Sequence Diagram

The TE0745 SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DCDC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

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Figure 4: Power-On Sequence

The Enable-Signal 'EN_PL' is permanently logic high in standard SC-CPLD firmware. The "Power Good"-signals 'PWR_PS_OK' and 'PWR_PL_OK' (latter low-active, extern pull-up needed) are available B2B-connector J2 (pins J2-139, J2-135) and on the SC-CPLD.

Power Rails

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Table 17: Differences between variants of Module TE0808TE0745-0402

Technical Specification

Absolute Maximum Ratings

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