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On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U9). The 125MHz PHY output clock (PHY_CLK125M) is routed to the B2B connector J2 pin 150.
| PHY Pin | ZYNQ PS | B2B | Notes |
|---|---|---|---|
| MDC/MDIO | MIO52, MIO53 | - | - |
| PHY LEDs | - | PHY_LED0: J2-144 | - |
| PHY_LED2 / INTn: | - | J2-148 | Active low interrupt line |
| PHY_CLK125M | - | J2-150 | 125 MHz Ethernet PHY clock out |
| CONFIG | - | - | Permanent high (PS_1.8V) |
| RESETn | MIO9 | - | Active low reset line |
| RGMII | MIO16..MIO27 | - | Reduced Gigabit Media Independent Interface |
| SGMII | - | - | Serial Gigabit Media Independent Interface |
| MDI | - | PHY_MDI0: J2-120 / J2-122 PHY_MDI1: J2-126 / J2-128 PHY_MDI2: J2-132 / J2-134 PHY_MDI3: J2-138 / J2-140 | Media Dependent Interface |
Table 9: Ethernet PHY interface connections
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USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 25.000000 MHz oscillator (U15).
| PHY Pin | ZYNQ Pin | B2B Name | Notes |
|---|---|---|---|
| ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY. |
| REFCLK | - | - | 52MHz from on board oscillator (U33). |
| REFSEL[0..2] | - | - | All pins set to GND selects the external reference clock frequency (52.000000 MHz). |
| RESETB | MIO7 | - | Active-low reset line. |
| CLKOUT | MIO36 | - | Set to high (1.8V VDDIO level) to select reference clock operation mode. |
| DP, DM | - | OTG_D_P, OTG_D_N, pin J2-149 / J2-151 | USB data lines. |
| CPEN | - | VBUS_V_EN, pin J2-141 | External USB power switch active-high enable signal. |
| VBUS | - | USB_VBUS, pin J2-145 | Connect to USB VBUS via a series of resistors, see reference schematics. |
| ID | - | OTG_ID, pin J2-143 | For an A-device connect to the ground. For a B-device, leave floating. |
Table 10: USB PHY interface connections
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| Parameter | Min | Max | Units | Notes | Reference Document | |
|---|---|---|---|---|---|---|
| PL_VIN | 3.3 | 4.5 | V | - | TI TPS720 data sheet | |
| PS_VIN | 3.3 | 6.0 | V | - | TI TPS82085 data sheet | |
| PS_3.3V | 3. | 1353 | 3.465 | V | - | 3.3V nominal ± 5% |
| VBAT_IN supply voltage | 2.7 | 5.5 | V | - | ISL12020MIRZ data sheet | |
PL I/O bank supply voltage for HR | 1.14 | 3.465 | V | - | Xilinx datasheet DS191 | |
PL I/O bank supply voltage for HP | 1.14 | 1.89 | V | - | Xilinx datasheet DS191 | |
| I/O input voltage for HR I/O banks | -0.20 | VCCO_X+0.20 | V | - | Xilinx datasheet DS191 | |
| I/O input voltage for HP I/O banks | -0.20 | VCCO_X+0.20 | V | - | Xilinx datasheet DS191 | |
| GT receiver (RXP/RXN) and transmitter (TXP/TXN) | (*) | (*) | V | (*) Check datasheet | Xilinx datasheet DS191 | |
| Voltage on Module JTAG pins | 3.135 | 3.6 | V | JTAG signals forwarded to Zynq module config bank 0 | MachX02 Family Data Sheet |
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