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Table 6: Default MIO Mapping
I2C Interface
The I2C interface on the B2B connector J2 pins 119 (I2C_33_SCL) and 121 (I2C_33_SDA) have PS_3.3V as a reference voltage.
Except the RTC (U24), all remaining I2C slave devices are operating with the reference voltage PS_1.8V via voltage level translating (3.3V ↔ 1.8V) I2C bus repeater (U17).
I2C addresses for on-board devices are listed in the table below:
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Gigabit Ethernet Interface
On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U9). The 125MHz PHY output clock (PHY_CLK125M) is routed to the B2B connector J2 pin 150.
| PHY Pin | ZYNQ PS | B2B | Notes |
|---|---|---|---|
| MDC/MDIO | MIO52, MIO53 | - | - |
| PHY LEDs | - | PHY_LED0: J2-144 | - |
| PHY_LED2 / INTn: | - | J2-148 | Active low interrupt line |
| PHY_CLK125M | - | J2-150 | 125 MHz Ethernet PHY clock out |
| CONFIG | - | - | Permanent high (PS_1.8V) |
| RESETn | MIO9 | - | Active low reset line |
| RGMII | MIO16..MIO27 | - | Reduced Gigabit Media Independent Interface |
| SGMII | - | - | Serial Gigabit Media Independent Interface |
| MDI | - | PHY_MDI0: J2-120 / J2-122 PHY_MDI1: J2-126 / J2-128 PHY_MDI2: J2-132 / J2-134 PHY_MDI3: J2-138 / J2-140 | Media Dependent Interface |
Table 7: Ethernet PHY interface connections
USB Interface
USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 25.000000 MHz oscillator (U15).
| PHY Pin | ZYNQ Pin | B2B Name | Notes |
|---|---|---|---|
| ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY. |
| REFCLK | - | - | 52MHz from on board oscillator (U33). |
| REFSEL[0..2] | - | - | All pins set to GND selects the external reference clock frequency (52.000000 MHz). |
| RESETB | MIO7 | - | Active-low reset line. |
| CLKOUT | MIO36 | - | Set to high (1.8V VDDIO level) to select reference clock operation mode. |
| DP, DM | - | OTG_D_P, OTG_D_N, pin J2-149 / J2-151 | USB data lines. |
| CPEN | - | VBUS_V_EN, pin J2-141 | External USB power switch active-high enable signal. |
| VBUS | - | USB_VBUS, pin J2-145 | Connect to USB VBUS via a series of resistors, see reference schematics. |
| ID | - | OTG_ID, pin J2-143 | For an A-device connect to the ground. For a B-device, leave floating. |
Table 8: USB PHY interface connections
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
I2C Interface
The I2C interface on the B2B connector J2 pins 119 (I2C_33_SCL) and 121 (I2C_33_SDA) have PS_3.3V as a reference voltage.
Except the RTC (U24), all remaining I2C slave devices are operating with the reference voltage PS_1.8V via voltage level translating (3.3V ↔ 1.8V) I2C bus repeater (U17).
I2C addresses for on-board devices are listed in the table below:
| I2C Device | I2C Address | Notes |
|---|---|---|
| Zynq chip U1, bank 500 (PS MIO), pins MIO10 (SCL), MIO11 (SDA) | User programmable | Configured as I2C by default |
| Quad programmable PLL clock generator U16: pins 12 (SCL), 19 (SDA) | 0x70 | - |
| MAC Address EEPROM U23, pins 1 (SCL), 3 (SDA) | 0x53 | - |
| SC CPLD U2, bank 2, pins 16 (SDA), 17 (SCL) | User programmable | - |
| RTC, U24 | 0x6F | - |
| RTC RAM, U24 | 0x57 | - |
Table 9: Module's I2C-interfaces overview
Boot Process
TE0745 module supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21.
The current boot mode will be set by the MIO pins MIO3...MIO5. The control line 'BOOTMODE' is connected to the 'MIO4' pin, 'BOOTMODE_1' to 'MIO5'.
Following table describes how to set the control lines to configure the desired boot mode:
| Boot Mode | MIO5 (BOOTMODE_1) | MIO4 (BOOTMODE) | MIO3 | Note |
|---|---|---|---|---|
JTAG | 0 | 0 | 0 | - |
| NOR | 0 | 0 | 1 | MIO3 pin is shared with QSPI Flash Memory (QSPI-DQ1) |
| NAND | 0 | 1 | 0 | - |
| QSPI Flash Memory | 1 | 0 | 0 | standard mode in current configuration |
| SD-Card | 1 | 1 | 0 | SD-Card on base board necessary |
Table 10: Selectable boot modes
On-board Peripherals
Flash
The TE0745 SoM is equipped with 32 MByte Flash memory for configuration and operation.
| Name | IC | ID | PS7 | MIO | Notes |
|---|---|---|---|---|---|
| SPI Flash | S25FL256SAGBHI20 | U14 | QSPI0 | MIO1..MIO6 | - |
MAC Address EEPROM
A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.
Table 7: Module's I2C-interfaces overview
Boot Process
TE0745 module supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21.
The current boot mode will be set by the MIO pins MIO3...MIO5. The control line 'BOOTMODE' is connected to the 'MIO4' pin, 'BOOTMODE_1' to 'MIO5'.
Following table describes how to set the control lines to configure the desired boot mode:
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MIO3
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JTAG
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Table 8: Selectable boot modes
On-board Peripherals
Flash
The TE0745 SoM is equipped with 32 MByte Flash memory for configuration and operation.
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Gigabit Ethernet Interface
On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U9). The 125MHz PHY output clock (PHY_CLK125M) is routed to the B2B connector J2 pin 150.
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PHY_LED0: J2-144
PHY_LED1: J2-146
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Table 9: Ethernet PHY interface connections
MAC Address EEPROM
A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.
USB Interface
USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 25.000000 MHz oscillator (U15).
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Table 10: USB PHY interface connections
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
RTC - Real Time Clock
An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I2C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD bank 3 pin 4.
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| Parameter | Min | Max | Units | Notes | Reference Document | |
|---|---|---|---|---|---|---|
| PL_VIN | 3.3 | 4.5 | V | - | TI TPS720 data sheet | |
| PS_VIN | 3.3 | 6.0 | V | - | TI TPS82085 data sheet | |
| PS_3.3V | 3. | 3135 | 3.465 | V | - | 3.3V nominal ± 5% |
| VBAT_IN supply voltage | 2.7 | 5.5 | V | - | ISL12020MIRZ data sheet | |
PL I/O bank supply voltage for HR | 1.14 | 3.465 | V | - | Xilinx datasheet DS191 | |
PL I/O bank supply voltage for HP | 1.14 | 1.89 | V | - | Xilinx datasheet DS191 | |
| I/O input voltage for HR I/O banks | -0.20 | VCCO_X+0.20 | V | - | Xilinx datasheet DS191 | |
| I/O input voltage for HP I/O banks | -0.20 | VCCO_X+0.20 | V | - | Xilinx datasheet DS191 | |
| GT receiver (RXP/RXN) and transmitter (TXP/TXN) | (*) | (*) | V | (*) Check datasheet | Xilinx datasheet DS191 | |
| Voltage on Module JTAG pins | 3.135 | 3.6 | V | JTAG signals forwarded to Zynq module config bank 0 | MachX02 Family Data Sheet |
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