Page History
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| Bank | Type | B2B Connector | I/O Signals | LVDS Pairs | Bank Voltage | Notes |
|---|---|---|---|---|---|---|
| 12 | HR | J1 | 50 | 24 | VCCIO_12 pins J1-54, J1-55 | Voltage range 1.2V to 3.3V |
| 13 | HR | J1 | 50 | 24 | VCCIO_13 pins J1-112, J1-113 | Voltage range 1.2V to 3.3V |
| 33 | HP | J3 | 50 | 24 | VCCIO_33 pins J3-115, J3-120 | Voltage range 1.2V to 1.8V |
| 34 | HP | J2 | 50 | 24 | VCCIO_34 pins J2-29, J2-30 | Voltage range 1.2V to 1.8V |
| 35 | HP | J2 | 50 | 24 | VCCIO_35 pins J2-87, J2-88 | Voltage range 1.2V to 1.8V |
| 500 | MIO | J2 | 5 | - | 1.8V- | MIO0, MIO12 ... MIO15, user configurable I/O's on B2B |
| 501 | MIO | J3 | 12 | - | 1.8V- | MIO40 ... MIO51, user configurable I/O's on B2B |
Table 2: Count, type and voltage range of SoC's PL and PS I/O banks pins available through B2B connectors.
All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.
For detailed information about the pin-out, please refer to the Pin-out Table.
MGT Lanes
The configuration of the I/O's MIO0, MIO12 ... MIO15 and MIO40 ... MIO51 are depending on the base-board peripherals connected to these pins.
MGT Lanes
The MGT bank signals of the SoC The MGT bank signals of the SoC are routed to the B2B connectors J1 and J3. There are 8 high-speed data lanes (Xilinx GTX transceivers) available composed as differential signaling pairs for both directions (RX/TX). On B2B connector J3 there are also clock input pins for MGT transceivers.
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| MIO | Function | Connected to | Notes | MIO | Function | Connected to | Notes | |||
|---|---|---|---|---|---|---|---|---|---|---|
| 0 | GPIO | J2-137, SC CPLD bank 2, pin 14 | User configurable I/O on B2B. | 16..27 | ETH0 | Ethernet PHY U7 | RGMII | |||
| 1 | QSPI0 | QSPI Flash Memory U14, pin C2 | SPI Flash-CS | 28..39 | USB0 | USB PHY U32 | ULPI | |||
| 2 | QSPI0 | QSPI Flash Memory U14, pin D3 | SPI Flash-DQ0 | 40 | - | J2-150 | User configurable I/O on B2B. | |||
| 3 | QSPI0 | QSPI Flash Memory U14, pin D2 | SPI Flash-DQ1 | 41 | - | J2-152 | User configurable I/O on B2B. | |||
| 4 | QSPI0 | QSPI Flash Memory U14, pin C4 | SPI Flash-DQ2 | 42 | - | J2-154 | User configurable I/O on B2B. | |||
| 5 | QSPI0 | QSPI Flash Memory U14, pin D4 | SPI Flash-DQ3 | 43 | - | J2-156 | User configurable I/O on B2B. | |||
| 6 | QSPI0 | QSPI Flash Memory U14, pin B2 | SPI Flash-SCK | 44 | - | J2-158 | User configurable I/O on B2B. | |||
| 7 | GPIO | USB PHY U32, pin 27 | Low active USB PHY Reset (pulled-up to PS_1.8V) | 45 | - | J2-160 | User configurable I/O on B2B. | |||
| 8 | GPIO | SC CPLD bank 2, pin 13 | User I/O (pulled-up to PS_1.8V) | 46 | - | J2-145 | User configurable I/O on B2B. | |||
| 9 | GPIO | Ethernet PHY U7, pin 16 | Ethernet PHY Reset | 47 | - | J2-147 | User configurable I/O on B2B. | |||
| 10 | I²C | SCL line I2C-interface | 1.8V ref. voltage | 48 | - | J2-149 | User configurable I/O on B2B. | |||
| 11 | I²C | SDA line I2C-interface | 1.8V ref. voltage | 49 | - | J2-151 | User configurable I/O on B2B. | |||
| 12 | - | J2-123 | User configurable I/O on B2B. | 50 | - | J2-153 | User configurable I/O on B2B. | |||
| 13 | - | J2-125 | User configurable I/O on B2B. | 51 | - | J2-155 | User configurable I/O on B2B. | |||
| 14 | - | J2-127 | User configurable I/O on B2B. | 52 | ETH0 | Ethernet PHY U7, pin 7 | MDC | |||
| 15 | - | J2-129 | User configurable I/O on B2B. | 53 | ETH0 | Ethernet PHY U7, pin 8 | MDIO |
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| 52 | ETH0 | Ethernet PHY U7, pin 7 | MDC | |||||
|---|---|---|---|---|---|---|---|---|
| 53 | ETH0 | Ethernet PHY U7, pin 8 | MDIO |
Table 6: Default MIO Mapping
Quad SPI Interface
Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1..6.
| MIO | Signal Name | U7 Pin |
|---|---|---|
| 1 | SPI-CS | C2 |
| 2 | SPI-DQ0/M0 | D3 |
| 3 | SPI-DQ1/M1 | D2 |
| 4 | SPI-DQ2/M2 | C4 |
| 5 | SPI-DQ3/M3 | D4 |
| 6 | SPI-SCK/M4 | B2 |
Gigabit Ethernet Interface
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| PHY Pin | ZYNQ Pin | B2B Name | Notes |
|---|---|---|---|
| ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY. |
| REFCLK | - | - | 52MHz from on board oscillator (U33). |
| REFSEL[0..2] | - | - | All pins set to GND selects the external reference clock frequency (52.000000 MHz). |
| RESETB | MIO7 | - | Active-low reset line. |
| CLKOUT | MIO36 | - | Set to logic high (1.8V VDDIO level) to select reference clock (oscillator U33) operation mode. |
| DP, DM | - | OTG_D_P, OTG_D_N, pin J2-149 / J2-151 | USB data lines. |
| CPEN | - | VBUS_V_EN, pin J2-141 | External USB power switch active-high enable signal. |
| VBUS | - | USB_VBUS, pin J2-145 | Connect to USB VBUS via a series of resistors, see reference schematics. |
| ID | - | OTG_ID, pin J2-143 | For an A-device connect to the ground. For a B-device, leave floating. |
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Table 9: Module's I2C-interfaces overview
Boot Process
TE0745 module supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21.
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