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Table 5: System Controller CPLD special purpose I/O pins

Default MIO Mapping

The configuration of the I/O's MIO12 - MIO15 and MIO40 - MIO51 are depending on the base-board peripherals connected to these pins.

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Table 6: Default MIO Mapping

Quad SPI Interface

Quad SPI Flash (U7U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... 6MIO6.

MIO	Signal Name	U7 Pin
1	SPI-CS	C2
2	SPI-DQ0/M0	D3
3	SPI-DQ1/M1	D2
4	SPI-DQ2/M2	C4
5	SPI-DQ3/M3	D4
6	SPI-SCK/M4	B2

Table 6: MIO-pin assignment of the Quad SPI Flash memory IC

Gigabit Ethernet Interface

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signallingsignaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U9). The 125MHz PHY output clock (PHY_CLK125M) is routed to the B2B connector J2 pin 150.

PHY Pin	ZYNQ PS	B2B	Notes
MDC/MDIO	MIO52, MIO53	-	-
PHY LEDs	-	PHY_LED0: J2-144 PHY_LED1: J2-146	-
PHY_LED2 / INTn:	-	J2-148	Active low interrupt line
PHY_CLK125M	-	J2-150	125 MHz Ethernet PHY clock out
CONFIG	-	-	Permanent high (PS_1.8V)
RESETn	MIO9	-	Active low reset line
RGMII	MIO16 ... MIO27	-	Reduced Gigabit Media Independent Interface
SGMII	-	-	Serial Gigabit Media Independent Interface
MDI	-	PHY_MDI0: J2-120 / J2-122 PHY_MDI1: J2-126 / J2-128 PHY_MDI2: J2-132 / J2-134 PHY_MDI3: J2-138 / J2-140	Media Dependent Interface

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PHY Pin	ZYNQ Pin	B2B Name	Notes
ULPI	MIO28 ..39. MIO39	-	Zynq USB0 MIO pins are connected to the PHY.
REFCLK	-	-	52MHz from on board oscillator (U33).
REFSEL[0..2]	-	-	All pins set to GND selects the external reference clock frequency (52.000000 MHz).
RESETB	MIO7	-	Active-low reset lineLow active USB PHY Reset (pulled-up to PS_1.8V).
CLKOUT	MIO36	-	Set to logic high to select reference clock (oscillator U33) operation mode.
DP, DM	-	OTG_D_P, OTG_D_N, pin J2-149 / J2-151	USB data lines.
CPEN	-	VBUS_V_EN, pin J2-141	External USB power switch active-high enable signal.
VBUS	-	USB_VBUS, pin J2-145	Connect to USB VBUS via a series of resistors, see reference schematics.
ID	-	OTG_ID, pin J2-143	For an A-device connect to the ground. For a B-device, leave floating.

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I2C Interface

The I²C interface on the B2B connector J2 pins 119 (I2C_33_SCL) and 121 (I2C_33_SDA) have PS_3.3V as a reference voltage.B2B connector J2 pins 119 (I2C_33_SCL) and 121 (I2C_33_SDA) have PS_3.3V as reference voltage.

The I²C bus works internally on module with reference voltage 1.8V, on the Zynq chip it is connected to the PS I²C interface via PS MIO bank 500, pins MIO10 and MIO11.

MIO	Signal Schematic Name	Notes
10	I2C_SCL	1.8V reference voltage
11	I2C_SDA	1.8V reference voltage

Table 9: MIO-pin assignment of the module's I²C interface

Except the RTC (U24), all remaining I²C slave devices are operating with the reference voltage PS_1.8V via voltage level translating (3.3V ↔ 1.8V) I²C bus repeater (U17).

I2C I²C addresses for on-board devices are listed in the table below:

I2C Device	I2C Address	Notes
Zynq chip U1, bank 500 (PS MIO), pins MIO10 (SCL), MIO11 (SDA)	User programmable	Configured as I²C by default
Quad programmable PLL clock generator U16: pins 12 (SCL), 19 (SDA)	0x70	-
MAC Address EEPROM U23, pins 1 (SCL), 3 (SDA)	0x53	-
SC CPLD U2, bank 2, pins 16 (SDA), 17 (SCL)	User programmable	-
RTC, U24	0x6F	-
RTC RAM, U24	0x57	-

Table 910: Module's I²C-interfaces overview

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Boot Mode	MIO5 (BOOTMODE_1)	MIO4 (BOOTMODE)	MIO3	Note
JTAG	0	0	0	-
NOR	0	0	1	MIO3 pin is shared with QSPI Flash Memory (QSPI-DQ1)
NAND	0	1	0	-
QSPI Flash Memory	1	0	0	standard mode in current configuration
SD-Card	1	1	0	SD-Card on base board necessary

Table 1011: Selectable boot modes

On-board Peripherals

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Si5338A (U13) Input	Signal Schematic Name	Note
IN1/IN2	CLKIN_P, CLKIN_N	Reference clock signal from B2B connector J3, pins J3-74, J3-76 (base board decoupling capacitors and termination resistor necessary).
IN3	reference clock signal from oscillator SiTime SiTime SiT8008BI (U21)	25.000000 MHz fixed frequency.
IN4/IN6	pins put to GND	LSB (pin 'IN4') of the default I²C-adress 0x70 not activated.
IN5	not connected	-
Si5338A (U13) Output	Signal Schematic Name	Note
CLK0 A/B	MGTCLK1_P, MGTCLK1_N	Reference clock signal to MGT bank 112, pins U6/U5 (100 nF decoupling capacitors).
CLK1 A/B	CLK1_P, CLK1_N	Clock signal routed to B2B connector, pins J3-80, J3-82.
CLK2 A/B	CLK2_P, CLK2_N	Clock signal routed to B2B connector, pins J3-86, J3-88.
CLK3 A/B	MGTCLK3_P, MGTCLK3_N	Reference clock signal to MGT bank 111, pins AA6/AA5 (100 nF decoupling capacitors).

Table 1112: Pin description of PLL clock generator Si5338A

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Clock Source	Schematic Name	Frequency	Clock Input Destination
SiTime SiT8008BI oscillator, U21	-	25.000000 MHz	Quad PLL clock generator U16, pin 3
SiTime SiT8008BI oscillator, U12	PS_CLK	33.333333 MHz	Bank 500 (MIO0 bank), pin B24
SiTime SiT8008BI oscillator, U23	OTG-RCLK	52.000000 MHz	USB 2.0 transceiver PHY U32, pin 26
SiTime SiT8008BI oscillator, U9	ETH_CLKIN	25.000000 MHz	Gigabit Ethernet PHY U7, pin 34

Table 1213: Clock sources overview

On-board LEDs

LED

Color

Connected to

Description and Notes

D1

Green

System Controller CPLD, bank 3, pin 5

System main status LED, blinking indicates system activity

D2

Red

Zynq chip (U1), bank 0 (config bank), 'DONE' (pin W9)

Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured.

This LED remains OFF if System Controller CPLD can not power up the PL supply voltage.

Table 1314: LEDs of the module

Power and Power-On Sequence

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Power Input Pin	Typical Current
PL_VIN	TBD*
PS_VIN	TBD*
PS_3.3V	TBD*

Table 1415: Maximum current of power supplies. *to be determined soon with reference design setup.

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Voltages on B2B Connectors	B2B J1 Pin	B2B J2 Pin	B2B J3 Pin	Input/ Output	Note
PL_VIN	147, 149, 151, 153, 155, 157, 159	-	-	Input	supply voltage
PS_VIN	-	154, 156, 158	-	Input	supply voltage
PS_3.3V	-	160	-	Input	supply voltage
VCCIO12	54, 55	-	-	Input	high range bank I/O voltage
VCCIO13	112, 113	-	-	Input	high range bank I/O voltage
VCCIO33	-	-	115, 120	Input	high performance bank I/O voltage
VCCIO34	29, 30		-	Input	high performance bank I/O voltage
VCCIO35	87, 88		-	Input	high performance bank I/O voltage
VBAT_IN	146	-	-	Input	RTC (battery-backed) supply voltage
PS_1.8V	-	130	-	Output	internal 1.8V voltage level (Process System supply)

Table 1516: Power rails of the SoC module on accessible connectors

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Bank	Schematic Name	Voltage	Voltage Range
0 (config)	VCCIO_0	PL_1.8V if R67 is equipped PS_1.8V if R68 is equipped	-
500 (MIO0)	PS_1.8V	1.8V	-
501 (MIO1)	PS_1.8V	1.8V	-
502 (DDR3)	1.35V	1.35V	-
12 HR	VCCIO_12	User	HR: 1.2V to 3.3V
13 HR	VCCIO_13	User	HR: 1.2V to 3.3V
33 HP	VCCIO_33	User	HP: 1.2V to 1.8V
34 HP	VCCIO_34	User	HP: 1.2V to 1.8V
35 HP	VCCIO_35	User	HP: 1.2V to 1.8V

Table 1617: Range of SoC module's bank voltages

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Module Variant	Zynq SoC	SoC Junction Temperature	Operating Temperature Range
TE0745-02-30-1I	XC7Z030-1FBG676I	–40°C to +100°C	Industrial
TE0745-02-35-1C	XC7Z035-1FBG676C	0°C to +85°C	Commercial
TE0745-02-45-1C	XC7Z045-1FBG676C	0°C to +85°C	Commercial
TE0745-02-45-2I	XC7Z045-2FBG676I	–40°C to +100°C	Industrial

Table 1718: Differences between variants of Module TE0745-02

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Trenz Electronic Documentation

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Old Version 65

New Version 66

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