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Table 7: Ethernet PHY interface connections

USB Interface

USB PHY PHY (U32) is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 2552.000000 MHz oscillator (U15U33).

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The I²C bus works internally on module with reference voltage 1.8V, on the Zynq chip it is connected to the PS I²C interface via PS MIO bank 500, pins MIO10 and MIO11.

Table 9: MIO-pin assignment of the module's I²C interface

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Table 11: Selectable boot modes

On-board Peripherals

Flash

The TE0745 SoM is equipped with 32 MByte Flash memory for configuration and operation.

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In delivery state of the SoM the boot mode depends on the configured SC-CPLD firmware. The current mode is set to boot from the QSPI Flash Memory.

On-board Peripherals

System Controller CPLD

Lattice Semiconductor MachXO2 (U2) ...

Quad SPI Flash Memory

On-board QSPI flash memory S25FL256S (U7) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

The TE0745 SoM is equipped with 32 MByte Flash memory for configuration and operation.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin G13 of the System Controller CPLD chip (U19).

Ethernet PHY to SC CPLD connections

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

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MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

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An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I²C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at ^I2C I²C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD bank 3 pin 4.

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Table 12: Pin description of PLL clock generator Si5338A

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Oscillators

The SoC module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

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