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BankTypeLane CountB2B ConnectorSchematic Names / Connector PinsMGT Bank's Reference Clock Inputs

111

not available at XC7Z030 Zynq SoC

GTX4J1

MGT_RX4_P, MGT_RX4_N, pins J1-23, J1-21
MGT_TX4_P, MGT_TX4_N, pins J1-22, J1-20

MGT_RX5_P, MGT_RX5_N, pins J1-17, J1-15
MGT_TX5_P, MGT_TX5_N, pins J1-16, J1-14

MGT_RX6_P, MGT_RX6_N, pins J1-11, J1-9
MGT_TX6_P, MGT_TX6_N, pins J1-10, J1-8

MGT_RX7_P, MGT_RX7_N, pins J1-3, J1-5
MGT_TX7_P, MGT_TX7_N, pins J1-4, J1-6

1 Reference clock MGT_CLK3 from programmable
quad clock generator U16 to bank's pins AA6/AA5.

1 Reference clock MGT_CLK2 from B2B connector J3
(pins J3-81, J3-83) to bank's pins W6/W5.

112GTX4J3

MGT_RX3_P, MGT_RX3_N, pins J3-68, J3-70
MGT_TX3_P, MGT_TX3_N, pins J3-69, J3-71

MGT_RX2_P, MGT_RX2_N, pins J3-62, J3-64
MGT_TX2_P, MGT_TX2_N, pins J3-63, J3-65

MGT_RX1_P, MGT_RX1_N, pins J3-56, J3-58
MGT_TX1_P, MGT_TX1_N, pins J3-57, J3-59

MGT_RX0_P, MGT_RX0_N, pins J3-50, J3-52
MGT_TX0_P, MGT_TX0_N, pins J3-51, J3-53

1 Reference clock MGT_CLK1 from programmable
quad clock generator U16 to bank's pins U6/U5.

1 Reference clock MGT_CLK0 from B2B connector J3
(pins J3-75, J3-77) to bank's pins R6/R5.

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