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Interfaces I/O Signal CountPin schematic Names / FMC PinsConnected toNotes
JTAG5

FMC_TCK, pin J5-D29

FMC_TMS, pin J5-D33

FMC_TDI, pin J5-D30

FMC_TDO, pin J5- D31

SC CPLD U17, bank 1

VCCIO: 3V3SB

TRST_L, pin J5-D34 pulled-up to 3V3_PER

I²C2

FMC_SCL, pin J5-C30

FMC_SDA, pin J5-C31

I²C - Switch U16

I²C-lines pulled-up to 3V3_PER

Control Lines3

FMC_PRSNT_M2C, pin J5-H2

FMC_PG_C2M, pin J5-D1 (3V3_PER pull-up)

FMC_PG_M2C, pin J5-F1 (3V3_PER pull-up)

FMC_CLK_DIR, pin J5-B1 (pulled-down to GND)

I²C-Switch U16 via I²C - I/O -Port- Expander U38

SC CPLD U39, bank 0

I²C-Switch U16 via I²C - I/O -Port- Expander U38

SC CPLD U17, bank 1

'PG' = 'Power Good'-signal

'C2M' = carrier to (mezzanine) module

'M2C' = (mezzanine) module to carrier

...

Following table contains the assignment of the MIO pins to the configured interfaces:

MIOConfigured asAlternateSystem Controller CPLDNotes
0..12Dual QSPI-Dual Flash Memory on TE0808 SoM; Bootable
13..23SD0: eMMC-eMMC Memory U2; Bootable
24, 25 -CPLD (U39) MUXED -
26..29PJTAG0-CPLD (U17 MUXEDBootable JTAG (PJTAG0) possible
30force reboot after FSBL-PLL config for PCIe -
CPLD (U39) MUXED -
31PCIe resetCPLD (U39) MUXEDSame as ZCU102-
32 -CPLD (U39) MUXED -
33PMU-CPLD (U39) MUXEDSame as ZCU102-
34..37DisplayPort Aux-CPLD (U39) MUXED -
38, 39I2C0- -
40, 41CAN1forwarded to PWRLED_P / LED_P
CPLD (U39) MUXED -
41---
42, 43UART0CPLD (U39) MUXED -
44I2C InterruptSD_WP to FPGA 
CPLD (U39) MUXED -
45..51SD1: SD-Bootable MikeoSD MikroSD / MMC Card
52..63USB0- -
64..75GEM3-Ethernet RGMII
76, 77MDC / MDIO -Ethernet RGMII

...

  • SATA (PS GT bank 505, MGT2 Lane)
  • Display-Port (PS GT bank 505, MGT3 Lane, only TX-pair routed)
  • PCI Express (PS GT bank 505, MGT0 Lane)

FunctionMGT LaneRequired Ref ClockClock SourceComment
PCIePS 0100 MHzSi5345 (CLK0 of prog. PLL on mounted SoM) -
USB3PS 1100 MHzOptional Oscillator U6 -
SATAPS 2150 MHzOscillator U23 -
DP.0PS 327 MHz--Display Port

Table 6:  PS GT Lane Assignment

...

Figure 4: TEBF0808 PS GT Bank 505 Interface

MGT Interfaces SFP+ and

...

FireFly

The TEBF0808 carrier board provides the high speed MGT interface connectors "SFP+" (Enhanced small form-factor pluggable) and Samtec "FireFly". Each of this connectors are capable of data transmission rates up  to 10 Gbit/s.

FunctionMGT LaneRequired Ref ClockClock SourceComment
FireFlyB128 MGT Lanes 0..3-- -
SFPB230 MGT Lane 2125 / 156.25 MHzSi5345 (CLK7 of prog. PLL on mounted SoM) -
SFPB230 MGT Lane 3125 / 156.25 MHzSi5345 (CLK7 of prog. PLL on mounted SoM) -

...

HeaderPin NameFunctionConnected toNotes
J10

Pin 1, HD LED+
Pin 3, HD LED-
Pin 2, PWRLED+
Pin 4, PWRLED-
Pin 5, GND
Pin 7, RSTSW
Pin 6, PWRSW
Pin 8, GND
Pin 9, +5V DC

HD LED Anode
HD LED Cathode
Power LED Anode
Power LED Cathode
Ground
Reset Switch
Power Switch
Ground
5V DC Supply

SC CPLD U39Reset und Power Switch-pins are also
connected to switch buttons S1 and S2
J9

Pin 1, PORT1L
Pin 3, PORT1R
Pin 9, PORT2L
Pin 5, PORT2R
Pin 7, SENS_SEND
Pin 2, GND

Microphone Jack Left
Microphone Jack Right
Audio Out Jack Left
Audio Out Jack Right
Jack Detect / Mic in
Ground
24-bit Audio Codec IC U3-
J23Pin 1, 3V3SB
Pin 4, S1
3.3V DC Supply
PC compatible Beeper
SC CPLD U39-
J26

Pin 1, GND
Pin 2, 12V
Pin 3, F1SENSE
Pin 4, F1PWM

Ground
12V DC Supply
RPM
PWM
SC CPLD U394-wire PWM FAN connector
J35

Pin 1, GND
Pin 2, 12V
Pin 3, F2SENSE
Pin 4, F2PWM

Ground
12V DC Supply
RPM
PWM
SC CPLD U39

4-wire PWM FAN connector

optional load switch U48 to turn off/on FAN
with pin F2_EN

J19

Pin 1, GND
Pin 2, 5V

Ground
5V DC Supply
Load Switch Q3 (5V DCDC)2-wire FAN connector

Fan off/on switchable by signal 'FAN_FMC_EN'
on SC CPLD U39

Table 8: PC compatible Headers

Figure 7: TEBF0808 PC Compatible Headers

...

Further JTAG interfaces of the TEBF0808 carrier board are the ARM JTAG 20-pin IDC connector J30 and on the FMC Connector J5. This JTAG interfaces are connected to the System Controller CPLD U17, hence the logical processing and forwarding of the JTAG signals depend on the SC CPLD firmware. The documentation of the firmware of the SC CPLD U17 contains detailed information on this matter.

On-board Peripherals

System Controller CPDLs

The TEBF0808 is equipped with two System Controller CPLDs with the schematic designators U17 and U39. The CPLDs are provided by Lattice Semiconductor LCMXO2-1200HC (MachXO2 Product Family).

The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

Image Removed

 

 

Power and Power-up Sequence

Boot Process

TE0745 module supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21.

The current boot mode will be set by the MIO pins MIO3...MIO5. The control line 'BOOTMODE' is connected to the 'MIO4' pin, 'BOOTMODE_1' to 'MIO5'.

Following table describes how to set the control lines to configure the desired boot mode:

Boot ModeMIO5 (BOOTMODE_1)MIO4 (BOOTMODE)

MIO3

Note

JTAG

000-
NOR001MIO3 pin is shared with QSPI Flash Memory (QSPI-DQ1)
NAND010-
QSPI Flash Memory100standard mode in current configuration
SD-Card110SD-Card on base board necessary

Table 11: Selectable boot modes

In delivery state of the SoM the boot mode depends on the configured SC-CPLD firmware. The current mode is set to boot from the QSPI Flash Memory.

On-board Peripherals

System Controller CPDLs

The TEBF0808 is equipped with two System Controller CPLDs - Lattice Semiconductor LCMXO2-1200HC (MachXO2 Product Family) - with the schematic designators U17 and U39.

The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

Both Sytem Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO and also Programmable Logic pins.

The functionalities and configuration of the pins depend on the CPLDs' firmware. The documentations of the firmware of SC CPLD U17 and SC CPLD U39 contains detailed information on this matter.

Following block diagram visualizes the connection of the SC CPLDs with the Zynq Ultrascale+ MPSoC via PS (MIO) and PL bank pins.

Image Added

Figure 8: TEBF0808 System Controller CPLDs

 

Programmable PLL Clock Generator and Reference Clock Oscillators

The TEBF0808 Carrier Board is equipped with a Silicon Labs I2C programmable quad PLL clock generator Si5338A (U35). It's output frequencies can be programmed by using the I2C bus with address 0x70.

A 25 MHz (U7) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.

Once running, the frequency and other parameters can be changed by programming the device using the I2C-bus connected through I²C switch U16 between the Zynq module (master) and reference clock signal generator (slave).

Si5338A (U13) InputSignal Schematic NameNote

IN1/IN2

CLK8_P, CLK8_N

Reference clock signal from Si5345 (CLK8 of prog. PLL on mounted SoM)

IN3

reference clock signal from oscillator SiTime SiT8008BI (U7)

25.000000 MHz fixed frequency.

IN4/IN6

pins put to GNDLSB (pin 'IN4') of the default I²C-adress 0x70 not activated.

IN5

not connected

-
Si5338A (U13) Output
Signal Schematic NameNote

CLK0 A/B

SC_CLK0

Reference clock signal to SC CPLD U17 (single-ended signaling)

CLK1 A/B

SC_CLK1

Reference clock signal to SC CPLD U17 (single-ended signaling)

negative complementary signal 'SC_CLK1_N' put out to SMA Coax J33

CLK2 A/B

FMCCLK2_P, FMCCLK2_N

Clock signal routed to FMC connector J5, pins J5-K4 / J5-K5

CLK3 A/B

FMCCLK3_P, FMCCLK3_N

Clock signal routed to FMC connector J5, pins J5-J2 / J5-J3

Table 9: Pin description of PLL clock generator Si5338A

Image Added

Figure 8: Clocking Configuration of TE0808 SoM on TEBF0808 Carrier Board

To configure the programmable PLL clock generator on the mounted TE0808 SoM, refer to the TRM of this SoM.

Note

Si5338 OTP ROM is not programmed by default at delivery, so it is customers responsibility to either configure Si5338 during FSBL or then use SiLabs programmer and burn the OTP ROM with customer fixed clock setup.

Si5345 OTP can only be programmed two times, as different user configurations may required different setup, TEBF0808 is normally shipped with blank OTP.
For more information Si5338 at SiLabs.

Oscillators

The TEBF0808 carrier board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:

Clock SourceSchematic NameFrequencyClock Input Destination
SiTime SiT8008BI oscillator, U21-25.000000 MHzQuad PLL clock generator U16, pin 3

SiTime SiT8008BI oscillator, U12

PS_CLK33.333333 MHzBank 500 (MIO0 bank), pin B24
SiTime SiT8008BI oscillator, U33OTG-RCLK52.000000 MHzUSB 2.0 transceiver PHY U32, pin 26
SiTime SiT8008BI oscillator, U9ETH_CLKIN25.000000 MHzGigabit Ethernet PHY U7, pin 34

Table 10: Reference clock signal oscillators

 

High-speed USB ULPI PHY

USB PHY (U32) is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

PHY PinZYNQ PinB2B NameNotes
ULPIMIO28 ... MIO39-Zynq USB0 MIO pins are connected to the PHY.
REFCLK--52MHz from on board oscillator (U33).
REFSEL[0..2]--All pins set to GND selects the external reference clock frequency (52.000000 MHz).
RESETBMIO7-Low active USB PHY Reset (pulled-up to PS_1.8V).
CLKOUTMIO36-Set to logic high to select reference clock (oscillator U33) operation mode.
DP, DM-OTG_D_P, OTG_D_N,
pin J2-149 / J2-151
USB data lines.
CPEN-VBUS_V_EN,
pin J2-141
External USB power switch active-high enable signal.
VBUS-USB_VBUS,
pin J2-145
Connect to USB VBUS via a series of resistors, see reference schematics.
ID-OTG_ID,
pin J2-143
For an A-device connect to the ground. For a B-device, leave floating.

Table 8: USB PHY interface connections

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U9). The 125MHz PHY output clock (PHY_CLK125M) is routed to the B2B connector J2 pin 150.

PHY PinZYNQ PSB2BNotes
MDC/MDIOMIO52, MIO53--
PHY LEDs-

PHY_LED0: J2-144
PHY_LED1: J2-146

-
PHY_LED2 / INTn:-J2-148Active low interrupt line
PHY_CLK125M-J2-150125 MHz Ethernet PHY clock out
CONFIG--Permanent logic high
RESETnMIO9-Active low reset line
RGMIIMIO16 ... MIO27-Reduced Gigabit Media Independent Interface
SGMII--Serial Gigabit Media Independent Interface
MDI-PHY_MDI0: J2-120 / J2-122
PHY_MDI1: J2-126 / J2-128
PHY_MDI2: J2-132 / J2-134
PHY_MDI3: J2-138 / J2-140
Media Dependent Interface

Table 7: Ethernet PHY interface connections

I2C Switches

The I2C interface on B2B connector J2 pins 119 (I2C_33_SCL) and 121 (I2C_33_SDA) have PS_3.3V as reference voltage.

The I2C bus works internally on module with reference voltage 1.8V, on the Zynq chip it is connected to the PS I2C interface via PS MIO bank 500, pins MIO10 and MIO11.

MIOSignal Schematic NameNotes
10I2C_SCL1.8V reference voltage
11I2C_SDA1.8V reference voltage

Table 9: MIO-pin assignment of the module's I2C interface

Except the RTC (U24), all I2C slave devices are operating with the reference voltage PS_1.8V via voltage level translating (3.3V ↔ 1.8V) I2C bus repeater (U17).

I2C addresses for on-board devices are listed in the table below:

I2C Device I2C AddressNotes
Zynq chip U1, bank 500 (PS MIO), pins MIO10 (SCL), MIO11 (SDA)User programmableConfigured as I2C by default
Quad programmable PLL clock generator U16: pins 12 (SCL), 19 (SDA)0x70-
MAC Address EEPROM U23, pins 1 (SCL), 3 (SDA)0x53-
SC CPLD U2, bank 2, pins 16 (SDA), 17 (SCL)User programmable-
RTC, U240x6F-
RTC RAM, U240x57-

Table 10:  Module's I2C-interfaces overview

System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

Quad SPI Flash Memory

On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Note

SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.

RTC - Real Time Clock

An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I2C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD bank 3 pin 4.

On-board LEDs

LED

ColorConnected toDescription and Notes
D1redDONE signal (PS Configuration Bank 503)This LED goes ON when power has been applied to the module and
stays ON until MPSoC's programmable logic is configured properly.

Table 14: LED's description

Power and Power-On Sequence

Image Added

Power Consumption

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power Input PinTypical Current
DCDCINTBD*
LP_DCDCTBD*
PL_DCINTBD*
PS_BATTTBD*

Table 15: Maximum current of power supplies. *to be determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended. For the lowest power consumption and highest efficiency of on board DC/DC regulators it is recommended to powering the module from one single 3.3V supply. Except 'PS_BATT', all input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The TE0808 module equipped with the Xilinx Zynq Ultrascale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq Ultrascale+ MPSoC has multiple power domains, whereby each power domain requires its own particular extern DCDC converters.

The Processing System contains three Power Domains:

  • Battery Power Domain (BBRAM and RTC)
  • Full-Power Domain (Application Processing Unit, DDR Controller, Graphics Processing Unit and High-Speed Connectivity)
  • Low-Power Domain (Real-Time Processing Unit, Security and Configuration Unit, Platform Management Unit, System Monitor and General Connectivity)

The fourth Power Domain is for the Programmable Logic (PL). If individual Power Domain control is not required, power rails can be shared between domains.

On the TE0808-04 SoM, following Power Domains can be powered up individually with power rails available on the B2B connectors:

  • Full-Power Domain, supplied by power rail 'DCDCIN'
  • Low-Power Domain, supplied by power rail 'LP_DCDC'
  • Programmable Logic, supplied by power rail 'PL_DCIN'
  • Battery Power Domain, supplied by power rail 'PS_BATT'

Each Power Domain has its own "Enabling"- and "Power Good"-signals. The power rail 'GT_DCDC' is necessary for generating the voltages for the Multi Gigabit Transceiver units of the Zynq Ultrascale+ MPSoC.

Power Distribution Dependencies

The power rails 'DCDCIN', 'LP_DCDC', 'PL_DCIN', 'PS_BATT' have to be powered up on the assigned pins of the B2B connectors as listed on the section "Power Rails". Except 'PS_BATT' (see section "Recommended Operation Conditions"), all power-rails can be powered up, with 3.3V power sources, also shared, if Power Domain control is not required.

There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DCDC converters, which power up further DCDC converters and the particular on-board voltages:

Image Added

Figure 3: Power Distribution Diagram

Note

Current rating of  Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Power-On Sequence Diagram

The TE0808 SoM meets the recommended criteria to power up the Xilinx Zynq Ultrascale+ MPSoC properly by keeping a specific sequence of enabling the on-board DCDC converters dedicated to the particular Power Domains and powering up the on-board voltages.

The on-board voltages of the TE0808 SoM will be powered-up in order of a determined sequence by activating the above-mentioned power rails and the Enable-Signals of the DCDC converters. The on-board voltages will be powered up at three steps.

  1. Low-Power Domain (LPD) and on-board Si5345A programmable clock generator supply voltage
  2. Programmable Logic (PL) and Full-Power Domain (FPD)
  3. GTH, PS GTR transceiver and DDR memory

Hence, those three power instances will be powered up consecutively and the Power-Good-Signals of the previous instance has to be asserted.

Following diagram clarifies the sequence of enabling the three power instances utilizing the DCDC converter control signals ('Enable', 'Power-Good'), which will power-up in descending order as listed in the blocks of the diagram.

Image Added

Figure 4: Power-On Sequence Utilizing DCDC Converter Control Signals

 

Warning
To avoid any damages to the MPSoC module, check for stabilized on-board voltages in steady state before powering up the MPSoC's I/O bank voltages VCCOx. All I/O's should be tri-stated during power-on sequence.

Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like bank's I/O voltages (VCCOx) can be powered up.

It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good"-signals are high, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0808 SoM.

Power Rails

Voltages on B2B
Connectors

B2B J1 PinB2B J2 PinB2B J3 PinB2B J4 Pin

Input/
Output

Note
PL_DCINJ1-151, J1-153, J1-157, J1-159---Input-
DCDCIN

-

J2-154, J2-156, J2-158, J2-160,
J2-153, J2-155, J2-157, J2-159

--Input-
LP_DCDC-J2-138, J2-140, J2-142, J2-144--Input-
PS_BATT-J2-125--Input-
GT_DCDC--J3-157, J3-158, J3-159, J3-160-Input-
PLL_3V3--J3-152-InputU5 (programmable PLL)
3.3V nominal input
SI_PLL_1V8--J3-151-OutputInternal voltage level
1.8V nominal output
PS_1V8-J2-99J3-148-Output

Internal voltage level
1.8V nominal output

PL_1V8J1-91, J1-121---Output

Internal voltage level
1.8V nominal output

DDR_1V2-J2-135--Output

Internal voltage level
1.2V nominal output

Table 17: Power rails of the MPSoC module on accessible connectors

Bank Voltages

BankTypeSchematic Name / B2B connector PinsVoltageReference Input VoltageVoltage Range
47HDVCCO47, pins J3-43, J3-44user-max. 3.3V
48HDVCCO48, pins J3-15, J3-16user-max. 3.3V
64HPVCCO64, J4-58, J4-106userVREF_64, pin J4-88max. 1.8V
65HPVCCO65, J4-69, J4-105userVREF_65, pin J4-15max. 1.8V
66HPVCCO66, J1-90, J1-120userVREF_66, pin J1-108max. 1.8V
500MIOPS_1V81.8V--
501MIOPS_1V81.8V--
502MIOPS_1V81.8V--
503CONFIGPS_1V81.8V--

Table 18: Range of MPSoC module's bank voltages

B2B connectors

Include Page
IN:SS5-ST5 connectors
IN:SS5-ST5 connectors

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Unit

Notes / Reference Document

PL_DCIN-0.37VTPS82085SIL / EN63A0QI data sheet
DCDCIN-0.37VTPS82085SIL / TPS51206 data sheet
LP_DCDC-0.34VTPS3106K33DBVR data sheet
GT_DCDC-0.37VTPS82085SIL data sheet
PS_BATT-0.52VXilinx DS925 data sheet
PLL_3V3-0.53.8VSi5345/44/42 data sheet
VCCO for HD I/O banks-0.53.4VXilinx DS925 data sheet
VCCO for HP I/O banks-0.52VXilinx DS925 data sheet
VREF-0.52VXilinx DS925 data sheet
I/O input voltage for HD I/O banks-0.55VCCO + 0.55VXilinx DS925 data sheet
I/O input voltage for HP I/O banks-0.55VCCO + 0.55VXilinx DS925 data sheet
PS I/O input voltage (MIO pins)-0.5VCCO_PSIO + 0.55VXilinx DS925 data sheet,
VCCO_PSIO 1.8V nominally

Receiver (RXP/RXN) and transmitter
(TXP/TXN) absolute input voltage

-0.51.2VXilinx DS925 data sheet

Voltage on input pins of
NC7S08P5X 2-Input AND Gate

-0.5VCC + 0.5VNC7S08P5X data sheet,
see schematic for VCC

Voltage on input pins (nMR) of
TPS3106K33DBVR Voltage Monitor, U41

-0.3VDD + 0.3V

TPS3106 data sheet,
VDD = LP_DCDC

"Enable"-signals on TPS82085SIL
('EN_PLL_PWR', 'EN_LPD')
-0.37VTPS82085SIL data sheet

Storage temperature (ambient)

-40

100

°C

ROHM Semiconductor SML-P11 Series data sheet
Note
Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

ParameterMinMaxUnitNotes / Reference Document
PL_DCIN2.56VEN63A0QI / TPS82085SIL data sheet
DCDCIN3.16VTPS82085SIL / TPS51206PSQ data sheet
LP_DCDC2.53.6VTPS82085SIL / TPS3106 data sheet
GT_DCDC2.56VTPS82085SIL data sheet
PS_BATT1.21.5VXilinx DS925 data sheet
PLL_3V33.143.47VSi5345/44/42 data sheet
3.3V typical
VCCO for HD I/O banks1.143.4VXilinx DS925 data sheet
VCCO for HP I/O banks0.951.9VXilinx DS925 data sheet
I/O input voltage for HD I/O banks.-0.2VCCO + 0.2VXilinx DS925 data sheet
I/O input voltage for HP I/O banks-0.2VCCO + 0.2VXilinx DS925 data sheet
PS I/O input voltage (MIO pins)-0.2VCCO_PSIO + 0.2VXilinx DS925 data sheet,
VCCO_PSIO 1.8V nominally
Voltage on input pins of
NC7S08P5X 2-Input AND Gate
0VCCV

NC7S08P5X data sheet,
see schematic for VCC

Voltage on input pin 'MR' of
TPS3106K33DBVR Voltage Monitor, U41

0VDDV

TPS3106 data sheet,
VDD = LP_DCDC

Note
Please check Xilinx datasheet DS925 for complete list of absolute maximum and recommended operating ratings.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Extended grade: 0°C to +85°C.

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

  • Module size: 52 mm × 76 mm.  Please download the assembly diagram for exact numbers

  • Mating height with standard connectors: 4mm

  • PCB thickness: 1.6mm

  • Highest part on PCB: approx. 3mm. Please download the step model for exact numbers

All dimensions are given in millimeters.

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Revision History

Hardware Revision History

 DateRevision

Notes

Link to PCNDocumentation Link
-04First production silicon--
-03Second ES production release-TE0808-03
2016-03-0902First ES production release-TE0808-02
-01Prototypes--

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

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Document Change History

 Date

Revision

ContributorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

John Hartfiel, Ali Naseri
  • PCB REV04 Initial release
  • update boot mode section
2017-02-06V1Jan KumannInitial document

Disclaimer

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