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Table 7: MGT lanes available on PCIe interface.

MGT Lanes

MGT (Multi Gigabit Transceiver) lane consists of one receive and one transmit (RX/TX) differential pairs, four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, FMC connector pin connection and FPGA pin connection information:

FPGA to FMC MGT lanes

Lane	Bank	Type	Signal Name	FMC Pin	FPGA Pin
0	117	GTH	DP0_M2C_P DP0_M2C_N DP0_C2M_P DP0_C2M_N	J2A-C6 J2A-C7 J2A-C2 J2A-C3	MGTHRXP0_117, N4 MGTHRXN0_117, N3 MGTHTXP0_117, M2 MGTHTXN0_117, M1
1	117	GTH	DP1_M2C_P DP1_M2C_N DP1_C2M_P DP1_C2M_N	J2A-A2 J2A-A3 J2A-A22 J2A-A23	MGTHRXP1_117, L4 MGTHRXN1_117, L3 MGTHTXP1_117, K2 MGTHTXN1_117, K1
2	117	GTH	DP2_M2C_P DP2_M2C_N DP2_C2M_P DP2_C2M_N	J2A-A6 J2A-A7 J2A-A26 J2A-A27	MGTHRXP2_117, K6 MGTHRXN2_117, K5 MGTHTXP2_117, H2 MGTHTXN2_117, H1
3	117	GTH	DP3_M2C_P DP3_M2C_N DP3_C2M_P DP3_C2M_N	J2A-A10 J2A-A11 J2A-A30 J2A-A31	MGTHRXP3_117, J4 MGTHRXN3_117, J3 MGTHTXP3_117, F2 MGTHTXN3_117, F1
4	118	GTH	DP4_M2C_P DP4_M2C_N DP4_C2M_P DP4_C2M_N	J2A-A14 J2A-A15 J2A-A34 J2A-A35	MGTHRXP0_118, G4 MGTHRXN0_118, G3 MGTHTXP0_118, D2 MGTHTXN0_118, D1
5	118	GTH	DP5_M2C_P DP5_M2C_N DP5_C2M_P DP5_C2M_N	J2A-A18 J2A-A19 J2A-A38 J2A-A39	MGTHRXP1_118, E4 MGTHRXN1_118, E3 MGTHTXP1_118, C4 MGTHTXN1_118, C3
6	118	GTH	DP6_M2C_P DP6_M2C_N DP6_C2M_P DP6_C2M_N	J2A-B16 J2A-B17 J2A-B36 J2A-B37	MGTHRXP2_118, D6 MGTHRXN2_118, D5 MGTHTXP2_118, B2 MGTHTXN2_118, B1
7	118	GTH	DP7_M2C_P DP7_M2C_N DP7_C2M_P DP7_C2M_N	J2A-B12 J2A-B13 J2A-B32 J2A-B33	MGTHRXP3_118, B6 MGTHRXN3_118, B5 MGTHTXP3_118, A4 MGTHTXN3_118, A3
8	116	GTH	DP8_M2C_P DP8_M2C_N DP8_C2M_P DP8_C2M_N	J2A-B8 J2A-B9 J2A-B28 J2A-B29	MGTHRXP2_116, U4 MGTHRXN2_116, U3 MGTHTXP2_116, T2 MGTHTXN2_116, T1
9	116	GTH	DP9_M2C_P DP9_M2C_N DP9_C2M_P DP9_C2M_N	J2A-B4 J2A-B5 J2A-B24 J2A-B25	MGTHRXP3_116, R4 MGTHRXN3_116, R3 MGTHTXP3_116, P2 MGTHTXN3_116, P1

Table 8: FPGA to FMC connector MGT lanes overview (continue on next page).

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FPGA to FMC MGT lanes (continued)

Lane	Bank	Type	Signal Name	FMC Pin	FPGA Pin
5	118	GTH	DP5_M2C_P DP5_M2C_N DP5_C2M_P DP5_C2M_N	J2A-A18 J2A-A19 J2A-A38 J2A-A39	MGTHRXP1_118, E4 MGTHRXN1_118, E3 MGTHTXP1_118, C4 MGTHTXN1_118, C3
6	118	GTH	DP6_M2C_P DP6_M2C_N DP6_C2M_P DP6_C2M_N	J2A-B16 J2A-B17 J2A-B36 J2A-B37	MGTHRXP2_118, D6 MGTHRXN2_118, D5 MGTHTXP2_118, B2 MGTHTXN2_118, B1
7	118	GTH	DP7_M2C_P DP7_M2C_N DP7_C2M_P DP7_C2M_N	J2A-B12 J2A-B13 J2A-B32 J2A-B33	MGTHRXP3_118, B6 MGTHRXN3_118, B5 MGTHTXP3_118, A4 MGTHTXN3_118, A3
8	116	GTH	DP8_M2C_P DP8_M2C_N DP8_C2M_P DP8_C2M_N	J2A-B8 J2A-B9 J2A-B28 J2A-B29	MGTHRXP2_116, U4 MGTHRXN2_116, U3 MGTHTXP2_116, T2 MGTHTXN2_116, T1
9	116	GTH	DP9_M2C_P DP9_M2C_N DP9_C2M_P DP9_C2M_N	J2A-B4 J2A-B5 J2A-B24 J2A-B25	MGTHRXP3_116, R4 MGTHRXN3_116, R3 MGTHTXP3_116, P2 MGTHTXN3_116, P1

Table 8: FPGA to FMC connector MGT lanes overview.

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JTAG Interfaces

TEC0330 board JTAG interfaces accessing the FPGA or the System Controller CPLD:

JTAG interface	JTAG signals schematic name	JTAG connector pins	Connected to
CPLD JTAG VCCIO: 3V3PCI Connector: J8	CPLD_JTAG_TMS	J8-1	SC CPLD, bank 0, pin 90
	CPLD_JTAG_TDI	J8-2	SC CPLD, bank 0, pin 94
	CPLD_JTAG_TDO	J8-3	SC CPLD, bank 0, pin 95
	CPLD_JTAG_TCK	J8-4	SC CPLD, bank 0, pin 91

FPGA JTAG VCCIO: 1V8 Connector: J9	FPTAFPGA_JTAG_TMS	J9-4	FPGA, bank 0, pin N9
	FPTAFPGA_JTAG_TCK	J9-6	FPGA, bank 0, pin M8
	FPTAFPGA_JTAG_TDO	J9-8	FPGA, bank 0, pin N8
	FPTAFPGA_JTAG_TDI	J9-10	FPGA, bank 0, pin L8

FMC JTAG VCCIO: 3.3VPCI Connector: J2	FMC_TRST	J2-D34	SC CPLD, bank 2, pin 36
	FMC_TCK	J2-D29	SC CPLD, bank 2, pin 27
	FMC_TMS	J2-D33	SC CPLD, bank 2, pin 28
	FMC_TDI	J2-D30	SC CPLD, bank 2, pin 31
	FMC_TDO	J2-D31	SC CPLD, bank 2, pin 32

Table 89: JTAG Interface on TEC0330 board.

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Interface signals schematic name	System Controller CPLD pin	DDR3 memory interface pin
DDR3_SDA	Bank 2, pin 48	Pin 200 (3V3PCI pull-up)
DDR3_SCL	Bank 2, pin 49	Pin 202 (3V3PCI pull-up)

Table 910: I²C-interface between SC CPLD and DDR3 SDRAM memory.

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CPLD bank	CPLD bank's VCCIO
0	3V3PCI
1	3V3PCI
2	3V3PCI
3	1V8

Table 1011: VCCIO voltages of CPLD banks.

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CPLD functionality	Interface	Designated CPLD pins	Connected to	Notes
I²C interface between on-board peripherals and FPGA	I²C	FPGA_IIC_SDA, pin 24 FPGA_IIC_SCL, pin 25 FPGA_IIC_OE, pin 19	FPGA bank 16, pin V29 FPGA bank 16, pin W29 FPGA bank 16, pin W26	VCCIO: 1V8, all with pull-up to 1V8. Following devices and connectors are linked to the FPGA_IIC I²C interface: DC-DC converter U3 and U4 (LT LTM4676) Programmable quad clock generator U13 FMC connector J2 PCIe connector J1 Note: FPGA_IIC_OE must kept high for I²C operation. For I²C slave device addresses refer to the component datasheets.
User I/Os External LVDS pairs	10 I/Os 5 x differential signaling pairs	EX0_P ... EX4_P EX0_N ... EX4_N	IDC header J7	Can also be used for single-ended signaling.
User I/Os Internal LVDS pairs	13 I/Os 6 x differential signaling pairs	FEX0_P ... FEX5_P FEX0_N ... FEX5_N FEX_DIR (single-ended I/O)	FPGA bank 18	VCCIO: 1V8 Can also be used for single-ended signaling. FPGA bank 18 has also reference clock input from FMC connector (CLK2, CLK3) and clock synthesizer U9 (FCLK). Internal signal assignment: FEX_DIR <= FMC_PRSNT_M2C_L
FPGA programming control and state	2 I/Os	DONE, pin 7 PROGRAM_B, pin 8	FPGA bank 0, pin V8 FPGA bank 0, pin U8	VCCIO: 1V8
I²C interface to programmable quad clock generator	I²C	PLL_SCL, pin 14 PLL_SDA, pin 15	U13, pin 12 U13, pin 19	VCCIO: 1V8 Only PLL_SDA has 1V8 pull-up.
Fan PWM control J4	2 I/Os	F1SENSE, pin 99 F1PWM, pin 98	J4-3 (active low) J4-4	Internal signal assignment: FEX_5_P <= F1SENSE FEX_5_N => F1PWM
Button S2	1 I/O	BUTTON, pin 77	Switch S2	Functionality depends on CPLD firmware, activating pin PROGRAM_B (active low) and LED1 in standard configuration.
LED1	1 I/O	LED1, pin 76	LED D1 (green)	Fast blinking, when FPGA is not programmed. Internal signal assignment: LED1 <= Button S2 or FEX0_P
PCIe control line RESET_B	1 I/O	PCIE_RSTB, pin 37	PCIe connector J1-A11 (33R serial resistor)	Internal signal assignment: FEX_4_N <= PCIE_RSTB
Control Interface to clock synthesizer U9 (TI LMK04828B)	SPI (3 I/Os), 4 I/Os	CLK_SYNTH_SDIO, pin 75 CLK_SYNTH_SCK, pin 74 CLK_SYNTH_RESET, pin 54 CLK_SYNTH_CS, pin 53 CLK_SYNTH_SYNC, pin 52 LMK_STAT0, pin 62 LMK_STAT1, pin 63	U9, pin 20 U9, pin 19 U9, pin 5 U9, pin 18 U9, pin 6 U9, pin 31 U9, pin 48	Pull up to 3V3PCI. Internal signal assignment: LMK_SCK <= FEX_1_P LMK_SDIO <= FEX_1_N LMK_CS <= FEX_3_P LMK_SYNC <= EX_3_N LMK_RESET <= FEX_4_P FEX_2_P => LMK_SDIO (FEX_2_N must be 0) LMK_STAT0 and LMK_STAT1 signals are not used.
Control Interface to DC-DC converters U3 and U4 (both LT LTM4676)	I²C (2 I/Os), 2 I/Os	LTM_SCL, pin 67 LTM_SDA, pin 66 LTM1_ALERT, pin 65 LTM2_ALERT, pin 64	U4, pin E6 and U3, pin E6 U4, pin D6 and U3, pin D6 U4, pin E5 U3, pin E5	3V3 pull-ups. LTM I²C interface is also accessible trough header J10. LTM1_Alert and LTM2_ALERT signals are not used.
Power-on sequence and monitoring	6 I/Os	EN_1V8, pin 58 PG_1V8, pin 59 EN_FMC_VADJ, pin 60 PG_FMC_VADJ, pin 61 EN_3V3, pin 51 PG_3V3, pin 57	U20, pin 27 U20, pin 28 U7, pin 27 U7, pin 28 U15, pin 27 U15, pin 28	Sequence of the supply voltages depend on the System Controller CPLD firmware. EN_1V8, EN_3V3 and EN_FMC_VADJ will be set simultaneously at start-up. PG signals will not be evaluated.

Table 1112: Overview of the System Controller CPLD functions.

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Clock Source	Schematic Name	Frequency	Clock destination
SMA coaxial connector, J3	CLK_SYNTH_CLKIN0_P, CLK_SYNTH_CLKIN0_N (GND)	User	Clock synthesizer U9, pins 37/38
RAKON P5146LF oscillator, U11	-	10.0 MHz	Clock synthesizer U9, pins 43/44
SiTime SiT8208 oscillator, U14	CLK_25MHz	25.0 MHz	Programmable quad clock generator U13, pin 3
FMC connector J2, pins H4/H5	CLK0_P, CLK0_N	User	FPGA bank 17, pins R28/R29
FMC connector J2, pins G2/G3	CLK1_P, CLK1_N	User	FPGA bank 17, pins P29/P30
FMC connector J2, pins K4/K5	CLK2_P, CLK2_N	User	FPGA bank 18, pins G30/G31
FMC connector J2, pins J2/J3	CLK3_P, CLK3_N	User	FPGA bank 18, pins H29/H30
FMC connector J2, pins D4/D5	GBTCLK0_M2C_P, GBTCLK0_M2C_N	User	FPGA bank 117, pins M6/M5
FMC connector J2, pins B20/B21	GBTCLK1_M2C_P, GBTCLK1_M2C_N	User	FPGA bank 117, pins P6/P5
PCIe interface J1, pins A13/A14	PCIE_CLK_P, PCIE_CLK_N	100 MHz (PCIe spec.)	FPGA bank 115, pins AD6/AD5

Table 1213: Clock generator sources overview.

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Si5338A (U13) input	Signal schematic name	Notes
IN1/IN2	CLKIN_5338_C_P, CLKIN_5338_C_N	Reference clock signal from clock synthesizer U9 (100 nF decoupling capacitors and 100Ω termination resistor)
IN3	Reference clock oscillator input, SiTime SiT8208AI (U14).	25.0 MHz fixed frequency
IN4/IN6	Connected to the GND.	LSB (pin 'IN4') of the default I²C-adress 0x70 is zero
IN5	Not connected	-
Si5338A (U13) output	Signal schematic name	Notes
CLK0 A/B	DDR3_CLK_P, DDR3_CLK_N	DDR3-RAM reference clock signal to FPGA bank 35
CLK1 A/B	MGTCLK_5338_C_P, MGTCLK_5338_C_N	Reference clock signal to FPGA bank 115 MGT (100 nF decoupling capacitors and 100Ω termination resistor)
CLK2 A/B	LMK_CLK_P, LMK_CLK_N	Input clock signal to clock synthesizer U9 (100 nF decoupling capacitors)
CLK3 A/B	MGTCLK2_5338_C_P, MGTCLK2_5338_C_N	Reference clock signal to FPGA bank 118 MGT (100 nF decoupling capacitors and 100Ω termination resistor)

Table 1314: I/O pin description of programmable clock generator Si5338A.

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LMK04828B (U9) input	signal schematic name	Note
Status_LD1, Status_LD2	LMK_STAT0, LMK_STAT1	Connected to System Controller CPLD, not implemented in current CPLD firmware
SPI interface and control lines	see section 'System controller CPLD'	The clock synthesizer can be controlled and programmed by the FPGA module via the SPI interface and control lines, which are by-passed through the System Controller CPLD
CLKin0, CLKin0*	CLK_SYNTH_CLKIN0_P, CLK_SYNTH_CLKIN0_N	Input reference clock signal via SMA coaxial connector J3, connected to CLKin0* via serial decoupling capacitor 100nF. CLKin0 to connected to GND via serial decoupling capacitor 100nF.
CLKin1, CLKin1*	CLK_SYNTH_CLKIN1_P, CLK_SYNTH_CLKIN1_N	Input reference clock signal from programmable quad clock generator Si5338A (U13) via serial decoupling capacitor 100nF.
OSCin, OSCin*	-	Signal from reference clock oscillator RAKON P51446LF, fixed to 10.0 MHz
LMK04828B (U9) output	signal schematic name	Note
DCLKout0, DCLKout0*	CLK_SYNTH_DCLKOUT0_P, CLK_SYNTH_DCLKOUT0_N	Reference clock signal to FPGA bank 15 pins AD29/AE29
SDCLKout1, SDCLKout1*	CLK_SYNTH_SDCLKOUT1_P, CLK_SYNTH_SDCLKOUT1_N	Reference clock signal to FPGA bank 15 pins AE31/AF31
DCLKout2, DCLKout2*	CLKIN_5338_P, CLKIN_5338_N	Reference clock signal to programmable quad clock generator Si5338A (U13) (100 nF decoupling capacitors and 100Ω termination resistor)
DCLKout4, DCLKout4*	CLK_SYNTH_DCLKOUT4_P, CLK_SYNTH_DCLKOUT4_N	Reference clock signal to FPGA bank 115 MGT, pins T6/T5
SDCLKout7, SDCLKout7*	CLK_SYNTH_SDCLKOUT7_P, CLK_SYNTH_SDCLKOUT7_N	Reference clock signal to FPGA bank 118 MGT, pins F6/F5
OSCout0, OSCout0*	CLK_SYNTH_CLKIN2_P, CLK_SYNTH_CLKIN2_N	Reference clock signal to FPGA bank 18, pins J30/J31 (100 nF decoupling capacitors)

Table 1415: Pin description of clock synthesizer TI LMK04828B.

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Power Input	Typical Current
12V (J5)	TBD
3V3PCI (J1)	TBD

Table 1516: Maximum current of power supplies. TBD - To Be Determined.

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Bank	Schematic Name	Voltage	Range	Note
0	1V8	1.8V	HP: 1.2V to 1.8V	Config bank (fixed to 1.8V) / JTAG interface
14	1V8	1.8V	HP: 1.2V to 1.8V	QSPI flash memory interface
15	1V8	1.8V	HP: 1.2V to 1.8V	Reference clock input
16	1V8	1.8V	HP: 1.2V to 1.8V	I²C interface of FPGA
17	1V8	1.8V	HP: 1.2V to 1.8V	Reference clock input
18	1V8	1.8V	HP: 1.2V to 1.8V	Reference clock input / I/O's to CPLD
34	VCC1V5	1.5V	HP: 1.2V to 1.8V	DDR3 memory interface
35	VCC1V5	1.5V	HP: 1.2V to 1.8V	DDR3 memory interface
36	VCC1V5	1.5V	HP: 1.2V to 1.8V	DDR3 memory interface
114 115 116 117 118	MGTAVCC_FPGA MGTVCCAUX_FPGA MGTAVTT_FPGA	1.0V 1.8V 1.2V	MGT bank supply voltage MGT bank auxiliary supply voltage MGT bank termination circuits voltage	MGT banks with Xilinx GTH transceiver units
19	1V8	1.8V	HP: 1.2V to 1.8V	I/Os routed to FMC, usable as LVDS pairs
37	1V8	1.8V	HP: 1.2V to 1.8V	I/Os routed to FMC, usable as LVDS pairs
38	1V8	1.8V	HP: 1.2V to 1.8V	I/Os routed to FMC, usable as LVDS pairs
39	VIO_B_FMC	user	HP: 1.2V to 1.8V	I/Os routed to FMC, usable as LVDS pairs

Table 1617: Range of FPGAs bank voltages.

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Connector / Pin	Voltage	Direction	Notes
J4, pin 2	12V (filtered)	Output	4-wire PWM fan connector supply voltage
J6, pin 2	5V (filtered)	Output	Cooling fan M1 supply voltage
J8, pin 6	3V3PCI	Output	VCCIO CPLD JTAG
J9, pin 2	1V8	Output	VCCIO FPGA JTAG
J2, pin C35 / C37	12V	Output	VCCIO FMC
J2, pin D32	3V3PCI	Output	VCCIO FMC
J2, pin D36 / D38 / D39 / D40	3V3FMC	Output	VCCIO FMC
J2, pin H1	VREF_A_M2C	Input	VREF voltage for bank 37 / 38
J2, pin K1	VREF_B_M2C	Input	VREF voltage for bank 39
J2, pin J39 / J40	VIO_B_FMC	Input	PL I/O voltage bank 39 (VCCO)
J2, pin H40 / G39 / F40 / E39	FMC_VADJ	Output	VCCIO FMC (fixed to 1.8V)
J1, pin A10 / A11 / B8	3V3PCI	Input	PCIe interface supply voltage
J5, pin 1 / 2 / 3	12V	Input	Main power supply connector

Table 1718: Power rails and corresponding connectors of the FPGA board.

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Parameter	Min	Max	Units	Notes	Notes
12V power supply voltage	11.4	12.6	V	12V ± 5 %	ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) standard
PL I/O voltage for HP banks	-0.55	VCCO_X + 0.55	V	-	Xilinx datasheet DS183
GTH transceivers	-0.5	1.26	V	-	Xilinx datasheet DS183
Voltage on System Controller CPLD pins	-0.3	3.6	V	-	MachXO2 family datasheet
Storage temperature	-55	+125	°C	-	MachXO2 family datasheet

Table 1819: Absolute maximum ratings.

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Parameter	Min	Max	Units	Notes	Reference Document
12V power supply voltage	11.4	12.6	V	12V ± 5 %	ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) standard
PL I/O voltage for HP banks	-0.2	VCCO_X + 0.2	V	-	Xilinx datasheet DS183
GTH transceivers	(*)	(*)	-	-	Xilinx datasheet DS183
Voltage on System Controller CPLD pins	3.135	3.6	V	-	MachXO2 family datasheet

Table 1920: Recommended operation conditions.

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Date	Revision	Notes	PCN	Documentation
-	03	First production release	-	-
2015-11-05	02	Prototype	-	-
-	01	Prototype	-	-

Table 2021: Hardware revision history.

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Date

Revision

Contributors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Jan Kumann

MGT Lanes section added
Fixed signal names in JTAG section.

2017-08-30

v.15

Jan Kumann

Block diagram changed.
Physical dimensions image changed.
New product images.
Corrections in content.
Template revision added.

2017-03-15

v.3

Ali Naseri

Initial TRM release.

Table 2122: Document change history.

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Trenz Electronic Documentation

Versions Compared

Old Version 16

New Version 17

Key

MGT Lanes

JTAG Interfaces