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Table 7: System Controller CPLD I/O pins.
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Quad SPI Interface
Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.
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Power supply with minimum current capability of 3A for system startup is recommended. The maximum Maximum power consumption of a module mainly depends on the design running on the FPGA. Xilinx provides a power estimator excel sheets to calculate power consumption. It 's is also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
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