Page History

...

• MPSoC: ZYNQ UltraScale+ ZU7EV 900-pin package
• Memory
  - 64bit DDR4, 8 GByte maximum
  - Dual SPI boot Flash in parallel, 512 MByte maximum
• User I/Os
  - 65 x PS MIOs, 48 x PL HD GPIOs,  156 x PL HP GPIOs (3 banks)
  - Serial transceivers: 4 x GTR + 16 x GTH
  - Transceiver clocks inputs and outputs
  - PLL clock generator inputs and outputs
• Si5345 - 10 output PLL
• All power supplies on board, single 3.3V power source required
  - 14 on-board DC-DC regulators and 13 LDOs
  - LP, FPLPD, FPD, PL separately controlled power domains
• Support for all boot modes (except NAND) and scenarios
• Support for any combination of PS connected peripherals
• Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
• B2B connectors: 4 x 160 pin

...

Main Components

1. Xilinx ZYNQ UltraScale+ ZU7EV-1FBVB900 MPSoC, U1
2. EN63A0QI
3. Xilinx ZYNQ UltraScale+ XCZU9EG MPSoC, U1
4. Low-power programmable oscillator @ 33.333333 MHz (PS_CLK), U32
5. Red LED (DONE), D1
6. 256Mx16 DDR4-2400 SDRAM, U12
7. 256Mx16 DDR4-2400 SDRAM, U9
8. 256Mx16 DDR4-2400 SDRAM, U2
9. 256Mx16 DDR4-2400 SDRAM, U3
10. 12A PowerSoC DC-DC converter, U4
11. Quartz crystal, Y1
12. TI TPS72018 LDO @1.8V, U6
13. TI TPS74401 LDO @0.9V, U14
14. TI TPS74401 LDO @1.2V, U28
15. TI TPS72018 LDO @1.8V, U6
16. Quarz Crystal @50.000MHz, Y1
17. LowLow-power programmable oscillator @ 25.000000 MHz (IN0 for U5), U25
18. 10-channel programmable PLL clock generator, U5
19. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
20. TI TPS74801 LDO @1.8V, U10
21. TI TPS74801 LDO @0.9V, U8
22. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U12
23. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U9
24. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U2
25. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U3
26. Ultra fine 0.50 mm pitch, Razor Beam™ Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2J3
27. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3J1
28. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
29. Quartz crystal, Y2
30. 256 Mbit serial NOR Flash memory, U7
31. J4
32. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
33. 1.8V, 512 Mbit QSPI flash memory ,U17
34. 1.8V, 512 Mbit QSPI flash memory, U7
35. TI TPS72018 LDO @1.8V, U27256 Mbit serial NOR Flash memory, U17

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module

...

The boot device and mode of the Zynq UltraScale+ MPSoC can be selected via 4 dedicated pins accessible on B2B connector J2:

Table 2: Boot mode pins on B2B connector J2.

Following boot modes are possible on the TE0808 UltraScale+ module by generating the corresponding 4-bit code by the pins PS_MODE0 ... PS_MODE3 (little-endian alignment):

Table 3: Selectable boot modes by dedicated boot mode pins.

For functional details see  ug1085 - Zynq UltraScale+ TRM (Boot Modes Section).

...

Following table lists the I/O-bank signals, which are routed from the MPSoC's PL and PS banks as LVDS pairs or single ended I/O's to the B2B connectors.

Table 4: B2B connector pin-outs of Table 4: B2B connector pin-outs of available PL and PS banks of the TE0807-01 03 SoM.

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

...

The Xilinx Zynq UltraScale+ MPSoC device used on the TE0807 module has 20 high-speed data lanes (Xilinx GTH / GTR transceiver). All of them are wired directly to B2B connector. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Table 4: MGT lanes

There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

...

Table 5: MGT reference clock sources

JTAG Interface

JTAG access is provided through the MPSoC's PS configuration bank 503 with bank voltage PS_1V8.

...

Table 4: B2B connector pin-out of JTAG interface.

Configuration Bank Control Signals

The Xilinx Zynq UltraScale+ MPSoC's PS configuration bank 503 control signal pins are accessible through B2B connector J2.

For further information about the particular control signals and how to use and evaluate them, refer to the  Xilinx Zynq UltraScale+ MPSoC TRM and UltraScale Architecture Configuration - User Guide.

...

4-bit boot mode pins.

For further information about the boot modes refer to the Xilinx Zynq UltraScale+ MPSoC TRM section 'Boot and Configuration'.

...

ERR_OUT signal is asserted for accidental loss of power, an error, or an exception in the MPSoC's Platform Management Unit (PMU).

ERR_STATUS indicates a secure lock-down state.

...

Table 5: B2B connector pin-out of MPSoC's PS configuration bank.

Analog Input

The Xilinx Zynq UltraScale+ MPSoC provides differential pairs for analog input values. The pins are exposed to B2B-connector J2.

...

Table 5: MGT lanes

There are 2 clock sources for the GTH and GTR transceivers. The clock inputs of the MGT transceivers are connected directly to the B2B connectors, so the clock can be provided by the carrier board. The second clock source is provided by the on-board clock generator Si5345A (U5). As there are no capacitive coupling of the data and clock lines that are connected to the B2B connectors, these may be required on the user’s PCB depending on the application.

Table 6: MGT reference clock sources

JTAG Interface

JTAG access is provided through the MPSoC's PS configuration bank 503 with bank voltage PS_1V8.

Table 7: B2B connector pin-out of JTAG interface.

Configuration Bank Control Signals

The Xilinx Zynq UltraScale+ MPSoC's PS configuration bank 503 control signal pins are accessible through B2B connector J2.

For further information about the particular control signals and how to use and evaluate them, refer to the  Xilinx Zynq UltraScale+ MPSoC TRM and UltraScale Architecture Configuration - User Guide.

Table 8: B2B connector pin-out of MPSoC's PS configuration bank.

Analog Input

The Xilinx Zynq UltraScale+ MPSoC provides differential pairs for analog input values. The pins are exposed to B2B-connector J2.

Table 9: B2B connector pin-out of analog input pins

Quad SPI Interface

Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.

Table 10: PS MIO pin assignment of the Quad SPI Flash memory ICs.

Default PS MIO Mapping

Table 11: TE0807-03

Table 6: B2B connector pin-out of analog input pins

Quad SPI Interface

Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.

...

Table 7: PS MIO pin assignment of the Quad SPI Flash memory ICs.

Default PS MIO Mapping

...

JM1-19

...

JM1-21

...

63

...

Table 8: TE0807-01 PS MIO mapping

On-board Peripherals

Flash

The TE0808 TE0807 SoM can be configured with max. 512 MByte Flash memory for configuration and operation.

Table 1012: Peripherals connected to the PS MIO pins.

DDR4 SDRAM

The TE0807-01 03 SoM is equipped with with four DDR4 -2400 SDRAM modules chips with a total of up to 8 GByte memory density. The SDRAM modules chips are connected to the Zynq MPSoC's PS DDR controller (bank 504) with a 64-bit 64bit wide data bus.

Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s.

...

Following table illustrates on-board Si5345A programmable clock multiplier chip inputs and outputs:

Table 13Table 11: Programmable PLL clock generator input/output.

...

The Si5345A programmable clock generator's control interface pins are exposed to B2B connector J2. For further information refer to the Si5345A data sheet.

Table 1214: B2B connector pin-out of Si5345A programmable clock generator.

Si5345 OTP can only be programmed two times, as different user configurations may required different setup TE0808 is normally shipped with blank OTP.
For more information refer to Si5345 at SiLabs.

Oscillators

The TE0808-04 SoM is equipped with two on-board oscillators to provide the Zynq's MPSoC's PS configuration bank 503 with reference clock signals.

...

Si5345 OTP can only be programmed two times, as different user configurations may required different setup TE0808 is normally shipped with blank OTP.
For more information refer to Si5345 at SiLabs.

Oscillators

The TE0808-04 SoM is equipped with two on-board oscillators to provide the Zynq's MPSoC's PS configuration bank 503 with reference clock signals.

Table 15: On-board osciallators

MAC Address EEPROMs

There is one Microchip 24AA025E48 serial EEPROMs (U11) present containing a globally unique 48-bit node address, which are compatible with EUI-48(TM) specification. The device are organized as two blocks of 128 x 8 Kbit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. The MAC address EEPROM accessible over I²C bus on B2B connector J2-92 (PLL_SDA)  / J2-90 (PLL_SCL)Table 13: Reference clock-signals to PS configuration bank 503.

On-board LEDs

Table 1416: LED's description.

Power and Power-On Sequence

...

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 1517: Maximum current of power supplies. *to be determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended. For the lowest power consumption and highest efficiency of on board DC/DC regulators it is recommended to powering the module from one single 3.3V supply. Except 'PS_BATT', all input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The TE0808 TE0807 module equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

...

The fourth Power Domain is for the Programmable Logic (PL). If individual Power Domain control is not required, power rails can be shared between domains.

On the TE0808-04 TE0807 SoM, following power domains can be powered up individually with power rails available on the B2B connectors:

...

See also Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0807 module.

...

The on-board voltages of the TE0808 TE0807 SoM will be powered-up in order of a determined sequence by activating the above-mentioned power rails and the Enable-Signals of the DC-DC converters. The on-board voltages will be powered up at three steps.

...

Operation Conditions of the DC-DC Converter Control Signals

The control signals have to be asserted on the B2B connector J2, whereby some of the Power-Good signals need external pull-up resistors.

Table 1618: Recommended operation conditions of DC-DC converter control signals.

...

Power Rails

Table 19Table 16: TE0807-01 03 power rails

Bank Voltages

Table 1720: TE0807-01 03 I/O bank voltages

See Xilinx Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.

...

Variants Currently In Production

Technical Specifications

Absolute Maximum Ratings

Table 1821: Module absolute maximum ratings

...

Recommended Operating Conditions

Table 1922: Recommended operating conditions

...

• Module size: 52 mm × 76 mm.  Please download the assembly diagram for exact numbers

• Mating height with standard connectors: 4mm5mm

• PCB thickness: 1.6mm

• Highest part on PCB: approx. 3mm. Please download the step model for exact numbers

...

Revision History

Hardware Revision History

Table 2023: Hardware revision history table

...

Document Change History

<!--
Generate new entry:
1.add new row below first
2.Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number must be the same as the Wiki document revision number
3.Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description.
  -->

...

Date

...

Revision

...

Contributors

...

Description

...

...

...

• initial document

3.Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description.
  -->

Table 24Table 21: Document change history

Disclaimer

...