Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.


Page properties
hiddentrue
idComments

Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"


DateVersionChangesAuthor
2023-12-143.1.17
  • updated according to Vivado 2023.2
ma
2023-06-133.1.16
  • Design flow:
    • added alternative programming files in Petalinux
  • added chapter FSBL Patch in Software Design - Petalinux
ma
2023-06-013.1.15
  • removed u-boot.dtb from Design flow
ma
2023-06-013.1.14
  • expandable lists for revision history and supported hardware
wh
2023-05-253.1.13
  • updated according to Vivado 2022.2
ma
2023-02-083.1.12
  • removed content of
    • Special FSBL for QSPI programming
ma
2022-08-243.1.11
  • Modification from link "available short link"
ma
2022-01-253.1.10
  • removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
  • corrected Boot Source File in Boot Script-File
ma
2022-01-143.1.9
  • extended notes for microblaze boot process with linux
  • add u.boot.dtb to petalinux notes
  • add dtb to prebuilt content
  • replace 20.2 with 21.2
jh
2021-06-283.1.8
  • added boot process for Microblaze
  • minor typos, formatting
ma
2021-06-013.1.7
  • carrier reference note
jh
2021-05-043.1.6
  • removed zynq_ from zynq_fsbl
ma
2021-04-283.1.5
  • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
  • minor typos, formatting
ma
2021-04-273.1.4
  • Version History
    • changed from list to table
  • Design flow
    • removed step 5 from Design flow
    • changed link from TE Board Part Files to Vivado Board Part Flow
    • changed cmd shell from picture to codeblock
    • added hidden template for "Copy PetaLinux build image files", depending from hardware
    • added hidden template for "Power on PCB", depending from hardware
  • Usage update of boot process
  • Requirements - Hardware
    • added "*used as reference" for hardware requirements
  • all
    • placed a horizontal separation line under each chapter heading
    • changed title-alignment for tables from left to center
  • all tables
    • added "<project folder>\board_files" in Vivado design sources
ma

3.1.3
  • Design Flow
    • formatting
  • Launch
    • formatting
ma

3.1.2
  • minor typing corrections
  • replaced SDK by Vitis
  • changed from / to \ for windows paths
  • replaced <design name> by <project folder>
  • added "" for path names
  • added boot.src description
  • added USB for programming
ma

3.1.1
  • swapped order from prebuilt files
  • minor typing corrections
  • removed Win OS path length from Design flow, added as caution in Design flow
ma

3.1
  • Fix problem with pdf export and side scroll bar
  • update 19.2 to 20.2
  • add prebuilt content option


3.0
  • add fix table of content
  • add table size as macro
  • removed page initial creator


Custom_table_size_100

Page properties
hiddentrue
idComments

Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

      • Scroll Title
        anchorTable_xyz
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



  • ...

Overview

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


Page properties
hiddentrue
idComments

Notes :

ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.
Wiki Resources page: http://trenz.org/te0820-info

Key Features

Page properties
hiddentrue
idComments

Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Vitis/Vivado 2023.2
  • PetaLinux
  • SD
  • ETH
  • USB
  • I2C
  • RTC
  • FMeter
  • MAC from EEPROM
  • User LED (PCB REV03 only)
  • Modified FSBL for SI5338 programming

Revision History

Page properties
hiddentrue
idComments

Notes :

  • add every update file on the download
  • add design changes on description
Expand
titleExpand List
Scroll Title
anchorTable_DRH
title-alignmentcenter
titleDesign Revision History

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateVivadoProject BuiltAuthorsDescription
2024-03-052023.2TE0820-test_board-vivado_2023.2-build_4_20240305102020.zip
TE0820-test_board_noprebuilt-vivado_2023.2-build_4_20240305102020.zip
Manuela Strücker
  • bugfix file_location.txt
  • update USB available in uboot
2024-02-232023.2TE0820-test_board-vivado_2023.2-build_4_20240222140518.zip
TE0820-test_board_noprebuilt-vivado_2023.2-build_4_20240222140518.zip
Manuela Strücker
  • 2023.2 release
  • new assembly variants
2023-06-222022.2TE0820-test_board-vivado_2022.2-build_2_20230622121437.zip
TE0820-test_board_noprebuilt-vivado_2022.2-build_2_20230622121437.zip
Manuela Strücker
  • 2022.2 release
  • new assembly variants
2023-03-242021.2.1TE0820-test_board-vivado_2021.2-build_20_20230324121549.zip
TE0820-test_board_noprebuilt-vivado_2021.2-build_20_20230324121549.zip
Manuela Strücker
  • new assembly variants
2022-09-282021.2.1TE0820-test_board-vivado_2021.2-build_17_20220928065907.zip
TE0820-test_board_noprebuilt-vivado_2021.2-build_17_20220928065907.zip
Manuela Strücker
  • bugfix fsbl generation
  • new assembly variants
2022-09-122021.2.1TE0820-test_board-vivado_2021.2-build_15_20220912132233.zip
TE0820-test_board_noprebuilt-vivado_2021.2-build_15_20220912132233.zip
Manuela Strücker
  • update board part files compatible to Vivado 2021.2.1
  • new assembly variants
2022-01-282021.2TE0820-test_board-vivado_2021.2-build_11_20220128090819.zip
TE0820-test_board_noprebuilt-vivado_2021.2-build_11_20220128090819.zip
Manuela Strücker
  • new assembly variants
2022-01-242021.2TE0820-test_board-vivado_2021.2-build_10_20220124111148.zip
TE0820-test_board_noprebuilt-vivado_2021.2-build_10_20220124111148.zip
John Hartfiel
  • adding missing u-boot device tree to the boot.bin
2022-01-142021.2TE0820-test_board-vivado_2021.2-build_8_20220114123035.zip
TE0820-test_board_noprebuilt-vivado_2021.2-build_8_20220114123035.zip
John Hartfiel
  • 2021.2 release
  • new assembly variants
  • remove  alle PCB Revision 02 variant with 1GB DDR
2021-06-012020.2TE0820-test_board-vivado_2020.2-build_5_20210601084124.zip
TE0820-test_board_noprebuilt-vivado_2020.2-build_5_20210601092528.zip
John Hartfiel
  • 2020.2 release
  • new assembly variants
2020-04-082019.2TE0820-test_board_noprebuilt-vivado_2019.2-build_10_20200408073458.zip
TE0820-test_board-vivado_2019.2-build_10_20200408073444.zip
John Hartfiel
  • script update
  • new assembly variants
2020-03-252019.2TE0820-test_board_noprebuilt-vivado_2019.2-build_8_20200325083817.zip
TE0820-test_board-vivado_2019.2-build_8_20200325083750.zip
John Hartfiel
  • script update
  • Board Part update (minor changes)
2020-01-222019.2TE0820-test_board_noprebuilt-vivado_2019.2-build_3_20200122154341.zip
TE0820-test_board-vivado_2019.2-build_3_20200122154318.zip
John Hartfiel
  • script update for linux user
2020-01-142019.2TE0820-test_board-vivado_2019.2-build_3_20200114081551.zip
TE0820-test_board_noprebuilt-vivado_2019.2-build_3_20200114081612.zip
John Hartfiel
  • add fsbl_flash binary
  • Vitis script updates (include linux domain and prebuilt linux files for vitis)
  • prebuilt binary export on selection guide
2019-12-192019.2TE0820-test_board-vivado_2019.2-build_1_20191219075647.zip
TE0820-test_board_noprebuilt-vivado_2019.2-build_1_20191219080228.zip
John Hartfiel
  • 2019.2 update
  • Vitis support
2019-10-292018.3TE0820-test_board_noprebuilt-vivado_2018.3-build_09_20191029071045.zip
TE0820-test_board-vivado_2018.3-build_09_20191029071028.zip
John Hartfiel
  • new assembly variants
2019-08-092018.3TE0820-test_board_noprebuilt-vivado_2018.3-build_07_20190809084040.zip
TE0820-test_board-vivado_2018.3-build_07_20190809083901.zip
John Hartfiel
  • bugfix fsbl (removed second PSU init)
2019-06-192018.3TE0820-test_board_noprebuilt-vivado_2018.3-build_06_20190619073300.zip
TE0820-test_board-vivado_2018.3-build_06_20190619073243.zip
John Hartfiel
  • new assembly variants
  • USB2 only (change PS IP and device tree)
  • FSBL changes
2019-04-012018.3TE0820-test_board_noprebuilt-vivado_2018.3-build_03_20190401130135.zip
TE0820-test_board-vivado_2018.3-build_03_20190401130123.zip
John Hartfiel
  • renamed ...D variants to ...A
2019-02-212018.3

TE0820-test_board_noprebuilt-vivado_2018.3-build_01_20190221103025.zip
TE0820-test_board-vivado_2018.3-build_01_20190221102913.zip

John Hartfiel
  • TE Script update
  • rework of the FSBLs
  • SI5338 CLKBuilder Pro Project
  • some additional Linux features
  • MAC from EEPROM
  • new assembly variants
  • remove special compiler flags, which was needed in 2018.2
2018-10-312018.2

TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20181031164506.zip

TE0820-test_board-vivado_2018.2-build_03_20181031164452.zip

John Hartfiel
  • new assembly variants
  • update optional petalinux startup init script
2018-09-122018.2TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20180912094615.zip
TE0820-test_board-vivado_2018.2-build_03_20180912094558.zip
John Hartfiel
  • correction:
    • TE0820-03-4EV-1EA has 2GB DDR, now 2GB instead of 1GB is initialised
    • small changes on DDR setup of TE0820-02-2EG-1EE
2018-08-152018.2TE0820-test_board-vivado_2018.2-build_01_20180706212937.zip
TE0820-test_board_noprebuilt-vivado_2018.2-build_01_20180706212952.zip
John Hartfiel
  • different design for REV03
  • small petalinux changes
  • IO renaming
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
2018-06-192017.4TE0820-test_board-vivado_2017.4-build_10_20180619160713.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_10_20180619160728.zip
John Hartfiel
  • bugfix board part files BANK1 MIO voltages
  • Add "dummy" PS USB3 parameter so solve problems with some USB2 devices
2018-05-242017.4

TE0820-test_board-vivado_2017.4-build_10_20180524151356.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_10_20180524151342.zip

John Hartfiel
  • solved Linux Flash issue
  • new assembly variant
2018-04-252017.4TE0820-test_board-vivado_2017.4-build_07_20180425134435.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_07_20180425134459.zip
John Hartfiel
  • new assembly variants
2018-02-062017.4TE0820-test_board-vivado_2017.4-build_06_20180206203359.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_06_20180206203414.zip
John Hartfiel
  • solved JTAG/Linux issue
2018-02-012017.4TE0820-test_board-vivado_2017.4-build_05_20180201084319.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180201094724.zip
John Hartfiel
  • board part csv update
2018-01-242017.4TE0820-test_board-vivado_2017.4-build_05_20180124085247.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180124085303.zip
John Hartfiel
  • rework board part files
  • solved USB, QSPI and PHY issue
2017-11-212017.2TE0820-test_board-vivado_2017.2-build_05_20171121160552.zip
TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171121160606.zip
John Hartfiel
  • solved SD SDX Cards Problem
  • Separate csv name for all assembly variants
2017-11-202017.2TE0820-test_board-vivado_2017.2-build_05_20171120162931.zip
TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171120162851.zip
John Hartfiel
  • solved SD WP Problem
2017-10-192017.2TE0820-test_board-vivado_2017.2-build_05_20171019104824.zip
TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171019104837.zip
John Hartfiel
  • initial release



Release Notes and Know Issues

Page properties
hiddentrue
idComments
Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if issue fixed


Scroll Title
anchorTable_KI
title-alignmentcenter
titleKnown Issues

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

IssuesDescriptionWorkaroundTo be fixed version
Uboot: Ethernet not presentEthernet in Uboot cannot be used due to no MAC address set (Error: ethernet@ff0e0000 address not set.)

please set CONFIG_NET_RANDOM_ETHADDR in petalinux-config -c u-boot

as a side effect, MAC address will be random in Linux also

2023.2 version
Xilinx SoftwareIncompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Requestuse corresponding board files for the Vivado versions--
Uboot did not startEffected Design:
TE0820-test_board-vivado_2020.2-build_5_20210601084124.zip
TE0820-test_board_noprebuilt-vivado_2020.2-build_5_20210601092528.zip
Use older version, this will be fixed as soon as possibleSolved with 20220124 update
Flash access on LinuxDevice tree is not correct on Linuxadd compatibility to "compatible “jedec,spi-nor”"Solved with 20180524 update
USB UART Terminal is blocked / SDK Debugging is blockedThis happens only with 2017.4 Linux , when JTAG connection is established on Vivado HW Manager.

Do not use HW Manager connection, or if debugging is necessary:

  1. Boot linux with usb terminal
  2. From the terminal: root root mount ifconfig eth0
  3. Open two new SSH terminals via ethernet: root root , run user application ...
  4. Exit and close the usb terminal
Solved with 20180206 update


Requirements

Software

Page properties
hiddentrue
idComments

Notes :

  • list of software which was used to generate the design


Scroll Title
anchorTable_SW
title-alignmentcenter
titleSoftware

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SoftwareVersionNote
Vitis2023.2needed, Vivado is included into Vitis installation
PetaLinux2023.2needed
SI ClockBuilder Pro---optional


Hardware

Page properties
hiddentrue
idComments

Notes :

  • list of software which was used to generate the design

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Expand
titleExpand List
Scroll Title
anchorTable_HWM
title-alignmentcenter
titleHardware Modules

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0820-ES1es1REV011GB64MB4GBNANot longer supported by vivado
TE0820-02-02CG-1E2cg_1e_1gbREV021GB64MB4GBNANot longer supported use 2020.2 or older
TE0820-02-02CG-1EA2cg_1e_1gbREV021GB128MB4GBNANot longer supported use 2020.2 or older
TE0820-02-02EG-1E2eg_1e_1gbREV021GB64MB4GBNANot longer supported use 2020.2 or older
TE0820-02-02EG-1E32eg_1e_1gbREV021GB64MB4GB2.5 mm connectorsNot longer supported use 2020.2 or older
TE0820-02-02EG-1EA2eg_1e_1gbREV021GB128MB4GBNANot longer supported use 2020.2 or older
TE0820-02-02EG-1EL2eg_1e_1gbREV021GB128MB4GB2.5 mm connectorsNot longer supported use 2020.2 or older
TE0820-02-03CG-1E3cg_1e_1gbREV021GB64MB4GBNANot longer supported use 2020.2 or older
TE0820-02-03CG-1EA3cg_1e_1gbREV021GB128MB4GBNANot longer supported use 2020.2 or older
TE0820-02-03EG-1E3eg_1e_1gbREV021GB64MB4GBNANot longer supported use 2020.2 or older
TE0820-02-03EG-1E33eg_1e_1gbREV021GB64MB4GB2.5 mm connectorsNot longer supported use 2020.2 or older
TE0820-02-03EG-1EA3eg_1e_1gbREV021GB128MB4GBNANot longer supported use 2020.2 or older
TE0820-02-03EG-1EL3eg_1e_1gbREV021GB128MB4GB2.5 mm connectorsNot longer supported use 2020.2 or older
TE0820-02-04CG-1EA4cg_1e_1gbREV021GB128MB4GBNANot longer supported use 2020.2 or older
TE0820-03-02CG-1EA2cg_1e_2gbREV032GB128MB4GBNANA
TE0820-03-02CG-1ED2cg_1e_2gbREV032GB128MB8GBNANA
TE0820-03-02EG-1EA2eg_1e_2gbREV032GB128MB4GBNANA
TE0820-03-02EG-1EL2eg_1e_2gbREV032GB128MB4GB2.5 mm connectorsNA
TE0820-03-03CG-1EA3cg_1e_2gbREV032GB128MB4GBNANA
TE0820-03-03EG-1EA3eg_1e_2gbREV032GB128MB4GBNANA
TE0820-03-03EG-1EL3eg_1e_2gbREV032GB128MB4GB2.5 mm connectorsNA
TE0820-03-04CG-1EA4cg_1e_2gbREV032GB128MB4GBNANA
TE0820-03-04EV-1EA4ev_1e_2gbREV032GB128MB4GBNANA
TE0820-03-2AE21FA2cg_1e_2gbREV032GB128MB8GBNANA
TE0820-03-2AI21FA2cg_1i_2gbREV032GB128MB8GBNANA
TE0820-03-2BE21FA2eg_1e_2gbREV032GB128MB8GBNANA
TE0820-03-2BE21FL*2eg_1e_2gbREV032GB128MB8GB2.5 mm connectorsNA
TE0820-03-2BI21FA2eg_1i_2gbREV032GB128MB8GBNANA
TE0820-03-2BI21FL2eg_1i_2gbREV032GB128MB8GB2.5 mm connectorsNA
TE0820-03-3AE21FA3cg_1e_2gbREV032GB128MB8GBNANA
TE0820-03-3AI210A3cg_1i_2gbREV032GB128MB0GBNANA
TE0820-03-3AI21FA3cg_1i_2gbREV032GB128MB8GBNANA
TE0820-03-3BE21FA3eg_1e_2gbREV032GB128MB8GBNANA
TE0820-03-3BE21FL3eg_1e_2gbREV032GB128MB8GB2.5 mm connectorsNA
TE0820-03-4AE21FA4cg_1e_2gbREV032GB128MB8GBNANA
TE0820-03-4AI21FI4cg_1i_x_2gbREV032GB128MB8GBwithout ETH PHYNA
TE0820-03-4DE21FA4ev_1e_2gbREV032GB128MB8GBNANA
TE0820-03-4DE21FC4ev_1e_2gbREV032GB128MB8GBwithout encryption NCNRNA
TE0820-03-4DE21FL4ev_1e_2gbREV032GB128MB8GB2.5 mm connectorsNA
TE0820-03-4DI21FA4ev_1i_2gbREV032GB128MB8GBNANA
TE0820-03-5DI21FA5ev_1i_2gbREV032GB128MB8GBNANA
TE0820-03-5DR21FA5ev_1q_2gbREV032GB128MB8GBNANA
TE0820-04-2AE21FA2cg_1e_2gbREV042GB128MB8GBNANA
TE0820-04-2AI21FA2cg_1i_2gbREV042GB128MB8GBNANA
TE0820-04-2AI21MC2cg_1i_2gbREV042GB128MB8GBNANA
TE0820-04-2BE21-V12eg_1e_2gbREV042GB128MB8GBNACustomised
TE0820-04-2BE21FA2eg_1e_2gbREV042GB128MB8GBNANA
TE0820-04-2BE21FAJ2eg_1e_2gbREV042GB128MB8GBwithout spacersNA
TE0820-04-2BE21FL2eg_1e_2gbREV042GB128MB8GB2.5 mm connectorsNA
TE0820-04-2BE21MA2eg_1e_2gbREV042GB128MB8GBNANA
TE0820-04-2BE21MAJ2eg_1e_2gbREV042GB128MB8GBNANA
TE0820-04-2BI21FA2eg_1i_2gbREV042GB128MB8GBNANA
TE0820-04-2BI21FL2eg_1i_2gbREV042GB128MB8GB2.5 mm connectorsNA
TE0820-04-2BI21MA2eg_1i_2gbREV042GB128MB8GBNANA
TE0820-04-2BI21ML2eg_1i_2gbREV042GB128MB8GBNANA
TE0820-04-3AE21FA3cg_1e_2gbREV042GB128MB8GBNANA
TE0820-04-3AE21MA3cg_1e_2gbREV042GB128MB8GBNAOther EMMC mfr
TE0820-04-3AI21FA3cg_1i_2gbREV042GB128MB8GBNANA
TE0820-04-3AI21FAT3cg_1i_2gbREV042GB128MB8GBNACustomer supplied
TE0820-04-3BE21FA3eg_1e_2gbREV042GB128MB8GBNANA
TE0820-04-3BE21FL3eg_1e_2gbREV042GB128MB8GB2.5 mm connectorsNA
TE0820-04-3BE21KA3eg_1e_2gbREV042GB128MB64GBNANA
TE0820-04-3BE21MA3eg_1e_2gbREV042GB128MB8GBNANA
TE0820-04-3BE21ML3eg_1e_2gbREV042GB128MB8GB2.5 mm connectorsOther EMMC mfr
TE0820-04-3BE21MLZ3eg_1e_2gbREV042GB128MB8GB2.5 mm connectorsOther EMMC mfr
TE0820-04-4AE21FA4cg_1e_2gbREV042GB128MB8GBNANA
TE0820-04-4AE21MA4cg_1e_2gbREV042GB128MB8GBNANA
TE0820-04-4AI21FI4cg_1i_x_2gbREV042GB128MB8GBwithout ETH PHYNA
TE0820-04-4BI21KL4eg_1i_2gbREV042GB128MB64GB2.5 mm connectorsNA
TE0820-04-4DE21FA4ev_1e_2gbREV042GB128MB8GBNANA
TE0820-04-4DE21FL4ev_1e_2gbREV042GB128MB8GB2.5 mm connectorsNA
TE0820-04-4DE21MA4ev_1e_2gbREV042GB128MB8GBNAOther EMMC mfr
TE0820-04-4DI21FA4ev_1i_2gbREV042GB128MB8GBNANA
TE0820-04-4DI21MA4ev_1i_2gbREV042GB128MB8GBNAOther EMMC mfr
TE0820-04-5DI21FA5ev_1i_2gbREV042GB128MB8GBNANA
TE0820-04-5DI21MA5ev_1i_2gbREV042GB128MB8GBNANA
TE0820-04-5DR21FA5ev_1q_2gbREV042GB128MB8GBNANA
TE0820-04-S0023eg_1e_2gbREV042GB128MB8GBNAOther EMMC mfr|Custom supplied TE0820-04-3BE21MA
TE0820-04-S002C12eg_1e_2gbREV042GB128MB8GBNACAO
TE0820-04-S0033eg_1e_2gbREV042GB128MB8GB2.5 mm connectorsOther EMMC mfr
TE0820-04-S0042eg_1e_2gbREV042GB128MB8GBNACAO
TE0820-04-S0054cg_1e_2gbREV042GB128MB8GBNAOther EMMC mfr|Custom supplied TE0820-04-4AE21MA
TE0820-04-S0064ev_1e_2gbREV042GB128MB8GBNACAO:Other EMMC mfr
TE0820-04-S0093eg_1e_2gbREV042GB128MB8GB2.5 mm connectorsOther EMMC mfr
TE0820-04-S0104ev_1e_2gbREV042GB128MB8GBNACAO:Other EMMC mfr
TE0820-04-S0133eg_1e_2gbREV042GB128MB8GB2.5 mm connectorsCAO:Other EMMC mfr
TE0820-04-S0163eg_1e_2gbREV042GB128MB8GB2.5 mm connectorsCAO:Other EMMC mfr
TE0820-04-S0184cg_1e_2gbREV042GB128MB8GBNACAO
TE0820-05-2AE21MA2cg_1e_2gbREV052GB128MB8GBNANA
TE0820-05-2AE21MAZ2cg_1e_2gbREV052GB128MB8GBNANA
TE0820-05-2AE81MA2cg_1e_2gbREV052GB128MB8GBNANA
TE0820-05-2AI21MA2cg_1i_2gbREV052GB128MB8GBNANA
TE0820-05-2AI81MA2cg_1i_2gbREV052GB128MB8GBNANA
TE0820-05-2BE21MA2eg_1e_2gbREV052GB128MB8GBNANA
TE0820-05-2BE21MAJ2eg_1e_2gbREV052GB128MB8GBNANA
TE0820-05-2BI21MA2eg_1i_2gbREV052GB128MB8GBNANA
TE0820-05-2BI81ML2eg_1i_2gbREV052GB128MB8GB2.5 mm connectorsNA
TE0820-05-3AE21MA3cg_1e_2gbREV052GB128MB8GBNANA
TE0820-05-3AE81MA3cg_1e_2gbREV052GB128MB8GBNANA
TE0820-05-3BE21MA3eg_1e_2gbREV052GB128MB8GBNANA
TE0820-05-3BE21MAZ3eg_1e_2gbREV052GB128MB8GBNANA
TE0820-05-3BE81MA3eg_1e_2gbREV052GB128MB8GBNANA
TE0820-05-3BE81ML3eg_1e_2gbREV052GB128MB8GB2.5 mm connectorsOther EMMC mfr
TE0820-05-3BI21ML3eg_1i_2gbREV052GB128MB8GB2.5 mm connectorsNA
TE0820-05-4AE21MA4cg_1e_2gbREV052GB128MB8GBNANA
TE0820-05-4AE81MA4cg_1e_2gbREV052GB128MB8GBNANA
TE0820-05-4AI21MI4cg_1i_x_2gbREV052GB128MB8GBwithout ETH PHYNA
TE0820-05-4BI21PL4eg_1i_2gbREV052GB128MB64GB2.5 mm connectorsNA
TE0820-05-4BI21PLZ4eg_1i_2gbREV052GB128MB64GB2.5 mm connectorsNA
TE0820-05-4DE21MA4ev_1e_2gbREV052GB128MB8GBNAOther EMMC mfr
TE0820-05-4DI21MA4ev_1i_2gbREV052GB128MB8GBNAOther EMMC mfr
TE0820-05-4DI81MA4ev_1i_2gbREV052GB128MB8GBNAOther EMMC mfr
TE0820-05-5DI21MA5ev_1i_2gbREV052GB128MB8GBNANA
TE0820-05-5DI81MA5ev_1i_2gbREV052GB128MB8GBNANA
TE0820-05-S002C14cg_1e_2gbREV052GB128MB8GBNACAO
TE0820-05-S0034ev_1e_2gbREV052GB128MB8GBNACAO
TE0820-05-S004C12eg_1e_2gbREV052GB128MB8GBNACAO
TE0820-05-S0053eg_1e_2gbREV052GB128MB8GBNACAO
TE0820-05-S008C12eg_1e_2gbREV052GB128MB8GBNACAO:without PLL
TE0820-05-S0132eg_1e_2gbREV052GB128MB8GBNACAO:without PLL
TE0820-05-S014C14cg_1e_2gbREV052GB128MB8GBNACAO
TE0820-05-S0163eg_1e_2gbREV052GB128MB8GBNACAO
TE0820-05-S017C12eg_1e_2gbREV052GB128MB8GBNACAO:without PLL
TE0820-05-S0183cg_1e_2gbREV052GB128MB8GBNACAO
TE0820-05-S0203eg_1e_2gbREV052GB128MB8GBNACAO
TE0820-05-S0223cg_1e_2gbREV052GB128MB8GBNACAO
TE0820-05-S024C12eg_1e_2gbREV052GB128MB8GBNACAO

*used as reference

Design supports following carriers:

Scroll Title
anchorTable_HWC
title-alignmentcenter
titleHardware Carrier

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Carrier ModelNotes
TE0701
TE0703*
TE0705
TE0706
TEB0707
TEBA0841
  • Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
  • No SD Slot available, pins goes to Pin Header
  • For TEBA0841 REV01, please contact TE support
TEF1002

*used as reference

Additional HW Requirements:

Scroll Title
anchorTable_AHW
title-alignmentcenter
titleAdditional Hardware

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct type
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI
CoolerIt's recommended to use cooler on ZynqMP device


Content

Page properties
hiddentrue
idComments

Notes :

  • content of the zip file

For general structure and of the reference design, see Project Delivery - AMD devices

Design Sources

Scroll Title
anchorTable_DS
title-alignmentcenter
titleDesign sources

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

TypeLocationNotes
Vivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration


Additional Sources

Scroll Title
anchorTable_ADS
title-alignmentcenter
titleAdditional design sources

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

TypeLocationNotes
SI5338<project folder>\misc\Si5338SI5338 Project with current PLL Configuration
init.sh<project folder>\misc\sd\Additional Initialization Script for Linux



Prebuilt

Page properties
hiddentrue
idComments

Notes :

  • prebuilt files
  • Template Table:

    • Scroll Title
      anchorTable_PF
      title-alignmentcenter
      titlePrebuilt files

      Scroll Table Layout
      orientationportrait
      sortDirectionASC
      repeatTableHeadersdefault
      style
      widths
      sortByColumn1
      sortEnabledfalse
      cellHighlightingtrue

      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      Boot Script-File*.scr

      Distro Boot Script file

      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems





Scroll Title
anchorTable_PF
title-alignmentcenter
titlePrebuilt files (only on ZIP with prebuilt content)

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Boot Script-File*.scr

Distro Boot Script file

DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Page properties
hiddentrue
idComments

Reference Design is available on:

Design Flow

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


Page properties
hiddentrue
idComments
Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Note

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

    Code Block
    languagebash
    themeMidnight
    title_create_win_setup.cmd/_create_linux_setup.sh
    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    --------------------------------------------------------------------
    -------------------------TE Reference Design---------------------------
    --------------------------------------------------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    ----
    Select (ex.:'0' for module selection guide):


  2. Press 0 and enter to start "Module Selection Guide"
  3. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note

      Note: Select correct one, see also Vivado Board Part Flow


  4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    Code Block
    languagepy
    themeMidnight
    titlerun on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
    TE::hw_build_design -export_prebuilt


    Info

    Using Vivado GUI is the same, except file export to prebuilt folder.


  5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"
    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

  6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr
  7. Generate Programming Files with Vitis
    1. Copy PetaLinux build image files to prebuilt folder
      1. copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
        Info

        "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"


        Page properties
        hiddentrue
        idComments

        This step depends on Xilinx Device/Hardware

        for Zynq-7000 series

        • copy u-boot.elf, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

        for ZynqMP

        • copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

        for Microblaze

        • ...



    2.  Generate Programming Files
      Code Block
      languagepy
      themeMidnight
      titlerun on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
      TE::sw_run_vitis -all
      TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


      Note

      TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis


  8. Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart

Launch

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


Page properties
hiddentrue
idComments

Note:

  • Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.

Get prebuilt boot binaries

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select create and open delivery binary folder

      Info

      Note: Folder "<project folder>/_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


QSPI-Boot mode

Option for Boot.bin on QSPI Flash and image.ub, and boot.scr on SD or USB.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

    Code Block
    languagepy
    themeMidnight
    titlerun on Vivado TCL (Script programs BOOT.bin on QSPI flash)
    TE::pr_program_flash -swapp u-boot
    TE::pr_program_flash -swapp hello_te0820 (optional)


    Note

    To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup


  3. Copy image.ub, and boot.scr on SD or USB
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  4. Set Boot Mode to QSPI-Boot and insert SD or USB.
    • Depends on Carrier, see carrier TRM.

SD-Boot mode

  1. Copy image.ub, boot.src and Boot.bin on SD
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)


    Info

    Note: See TRM of the Carrier, which is used.


    Tip

    Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
    The boot options described above describe the common boot processes for this hardware; other boot options are possible.
    For more information see Distro Boot with Boot.scr


  4. Power On PCB

    Expand
    titleboot process

    1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    Page properties
    hiddentrue
    idComments

    This step depends on Xilinx Device/Hardware

    for Zynq-7000 series

    1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    for ZynqMP???

    1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

    for Microblaze with Linux

    1. FPGA Loads Bitfile from Flash,

    2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available)

    3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),

    4. U-boot loads Linux from QSPI Flash into DDR


    for native FPGA

    ...


Linux

  1. Open Serial Console (e.g. putty)
    • Speed: 115200
    • select COM Port

      Info

      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)


  2. Linux Console:

    Info

    Note: Wait until Linux boot finished


  3. You can use Linux shell now.

    Code Block
    languagebash
    themeMidnight
    i2cdetect -y -r 0	(check I2C 0 Bus)
    dmesg | grep rtc	(RTC check)
    udhcpc				(ETH0 check)
    lsusb				(USB check)


  4. Option Features

    • Webserver to get access to Zynq
      • insert IP on web browser to start web interface
    • init.sh scripts
      • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")


Vivado HW Manager

Page properties
hiddentrue
idComments

Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only

    SI5338_CLK0 Counter: 

    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

  • Control:
    • User LED (PCB REV03 and newer)
  • Monitoring:
    • SI5338_CLK0 Counter: 
      • Set radix from VIO signals to unsigned integer.
        Note: Frequency Counter is inaccurate and displayed unit is Hz
      • SI5338 CLK is configured to 200MHz by default.


PCB REV03 Design:

Scroll Title
anchorFigure_VHM
title-alignmentcenter
titleVivado Hardware Manager
Image Added


System Design - Vivado

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


Page properties
hiddentrue
idComments

Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design

PCB REV03

Scroll Title
anchorFigure_BD
title-alignmentcenter
titleBlock Design PCB REV03

Image Added

PS Interfaces

Activated interfaces:

TypeNote
DDR
QSPIMIO
SD0MIO
SD1MIO
I2C0MIO
UART0MIO
GPIO0MIO
SWDT0..1
TTC0..3
GEM3MIO
USB0MIO, USB2 only


Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design

Design specific constrain

Code Block
languageruby
title_i_io.xdc
set_property PACKAGE_PIN K9 [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property DIFF_TERM TRUE [get_ports {SI5338_CLK0_D_clk_p[0]}]

set_property PACKAGE_PIN H1 [get_ports {x0[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x0[0]}]
set_property PACKAGE_PIN J1 [get_ports {x1[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x1[0]}]

Software Design - Vitis

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


Page properties
hiddentrue
idComments
Note:
  • optional chapter separate

  • sections for different apps

For Vitis project creation, follow instructions from:

Vitis

Application

Page properties
hiddentrue
idComments

----------------------------------------------------------

FPGA Example

----------------------------------------------------------

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2023.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2023.2 xilisf_v5_11

  • Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

----------------------------------------------------------

fsbl

TE modified 2023.2 FSBL

General:

  • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY


----------------------------------------------------------

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2023.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

----------------------------------------------------------

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Template location: "<project folder>\sw_lib\sw_apps\"

zynqmp_fsbl

TE modified 2023.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_pmufw

Xilinx default PMU firmware.

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design - PetaLinux

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


Page properties
hiddentrue
idComments
Note:
  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"

For PetaLinux installation and project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

  • select SD default instead of eMMC:
    • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
  • add new flash partition for bootscr and sizing
    • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
    • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x2000000
    • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x40000
    • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
    • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
  • Identification
    • CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
    • CONFIG_SUBSYSTEM_PRODUCT="TE0820"

U-Boot

Start with petalinux-config -c u-boot
Changes:

  • MAC from eeprom together with uboot and device tree settings:
    • CONFIG_ENV_OVERWRITE=y
    • CONFIG_NVMEM=y
    • CONFIG_DM_RTC=y    (needed for nvmem driver because of bug in uboot)
  • Boot Modes:
    • CONFIG_QSPI_BOOT=y
    • CONFIG_SD_BOOT=y
    • CONFIG_ENV_IS_IN_FAT is not set
    • CONFIG_ENV_IS_IN_NAND is not set
    • CONFIG_ENV_IS_IN_SPI_FLASH is not set
    • CONFIG_BOOT_SCRIPT_OFFSET=0x2A40000
  • Identification
    • CONFIG_IDENT_STRING=" TE0820"

Change platform-top.h:

Code Block
languagejs
#include <configs/xilinx_zynqmp.h> #no changes

Device Tree

Code Block
languagejs
titleproject-spec\meta-user\recipes-bsp\device-tree\files\system-user.dtsi
/include/ "system-conf.dtsi"


/*-------------------- SD0 eMMC ----------------*/
&sdhci0 {
    // disable-wp;
    no-1-8-v;
};


/*-------------------- SD1 sd2.0 ----------------*/
&sdhci1 {
    disable-wp;
    no-1-8-v;
};


/*-------------------- USB 2.0 only ----------------*/
&usb0 {
    status = "okay";
    clock-names = "bus_clk";
    clocks = <&zynqmp_clk USB0_BUS_REF>;
    assigned-clocks = <&zynqmp_clk USB0_BUS_REF>;
};


&dwc3_0 {
    dr_mode = "host";
};
 

/*------------------ ETH PHY --------------------*/
&gem3 {
    //required otherwise petalinux gives a static address here
    /delete-property/ local-mac-address;
    phy-handle = <&phy0>;
    
    nvmem-cells = <&eth0_addr>;
    nvmem-cell-names = "mac-address";
    
    phy0: phy0@1 {
        device_type = "ethernet-phy";
        reg = <1>;
    };
};


/*------------------ QSPI -------------------- */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
        
        spi-rx-bus-width = <4>;
        spi-tx-bus-width = <4>;
        spi-max-frequency = <90000000>;
    };
};


/*------------------ I2C --------------------*/
&i2c0 {
    eeprom: eeprom@50 {
        compatible = "microchip,24aa025", "atmel,24c02";
        reg = <0x50>;
            
            #address-cells = <1>;
            #size-cells = <1>;
            eth0_addr: eth-mac-addr@FA {
              reg = <0xFA 0x06>;
            };
        };
};
  

Kernel

Start with petalinux-config -c kernel

Changes:

  • Only needed to fix JTAG Debug issue:

    • CONFIG_CPU_FREQ is not set

Rootfs

Start with petalinux-config -c rootfs

Changes:

  • for web server app:
    • CONFIG_busybox-httpd=y
  • For additional test tools only:
    • CONFIG_i2c-tools=y
    • CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
  • For auto login:
    • CONFIG_imagefeature-serial-autologin-root=y

FSBL patch (alternative for vitis fsbl trenz patch)

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"

Petalinux Troubleshoot#Petalinux2023.2

Applications

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application suitable for Zynq access. Need busybox-httpd

Additional Software

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


Page properties
hiddentrue
idComments
Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:

SI5338

File location "<project folder>\misc\Si5338\Si5338-*.slabtimeproj"

General documentation how you work with these project will be available on Si5338

Appx. A: Change History and Legal Notices

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue

Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

Page properties
hiddentrue
idComments
  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


Scroll Title
anchorTable_dch
title-alignmentcenter
titleDocument change history.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
widths2*,*,3*,4*
sortByColumn1
sortEnabledfalse
cellHighlightingtrue


DateDocument RevisionAuthorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
current-version
current-version
prefixv.

Page info
modified-user
modified-user

  • bugfix file_location.txt
  • update USB available in uboot
2024-02-23v.78Manuela Strücker
  • 2023.2 update
  • new assembly variants
2024-02-13v.77Markus Kirberg
  • update Release notes and known issues 
2023-06-22v.76Manuela Strücker
  • 2022.2 update
  • new assembly variants
2023-03-28v.75Manuela Strücker
  • new assembly variants
2022-09-28v.74Manuela Strücker
  • bugfix fsbl generation
  • new assembly variants
2022-09-12v.73Manuela Strücker
  • update board part files compatible to Vivado 2021.2.1
  • new assembly variants
2022-09-06v.72

Manuela Strücker

  • new assembly variants
2022-01-26v.70John Hartfiel
  • add missing uboot notes
2022-01-24v.68John Hartfiel
  • Add new delivery design with uboot bugfix
2022-01-21v.67John Hartfiel
  • Add Known issues
2022-01-14v.66John Hartfiel
  • 2021.2 release
2021-06-09v.65Manuela Strücker
  • document style update
2021-06-01v.64John Hartfiel
  • 2020.2 update
  • new assembly variants
  • document style update
2020-05-07v.62John Hartfiel
  • update programming section
2020-04-08v.61John Hartfiel
  • script update
  • new assembly variants
2020-03-25v.60John Hartfiel
  • script update
2020-01-21v.59John Hartfiel
  • Script update for linux user
2020-01-14v.58John Hartfiel
  • Script update, new features
  • doc update
  • add missing binary files
2019-12-19v.57John Hartfiel
  • 2019.2 release
2019-10-29v.56John Hartfiel
  • new assembly variants
2019-08-09v.55John Hartfiel
  • bugfix fsbl
2019-06-19v.54John Hartfiel
  • design changes
  • new variants
2019-04-01v.53John Hartfiel
  • some notes
  • renamed ..D variants to ...A

2018-09-21

v.47John Hartfiel
  • 2018.3 release finished (include design reworks)

2018-10-31

v.43John Hartfiel
  • Update Design files for 2GB variants
  • rebuilt petalinux for optional init script

2018-09-12

v.41John Hartfiel
  • Update Design files for 2GB variants

2018-07-11

v.40John Hartfiel
  • add notes to ES1

2018-07-06

v.38John Hartfiel
  • 2018.2 release finished

2018-06-19

v.34John Hartfiel
  • Design Files Update

2018-02-13

v.29John Hartfiel
  • Design Files Update
2018-02-06v.27John Hartfiel
  • Design Files Update
2018-01-29v.26John Hartfiel
  • Update Known Issues
2018-01-24v.25John Hartfiel
  • Release 2017.4
2018-01-10v.24John Hartfiel
  • Update Known Issues
2017-12-20v.23John Hartfiel
  • Typo correction
  • Update HW Module Table Description
2017-11-21

v.19

John Hartfiel
  • Design Update
2017-11-20v.18John Hartfiel
  • Design Update
HTML
<!--
Template Revision 1.0
Basic Notes
 - export PDF to download, if vivado revision is changed!
 - Template is for different design and SDSoC and examples, remove unused or wrong description!
 -->
Scroll Only (inline)
Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation
Scroll pdf ignore

Table of contents

Table of Contents
outlinetrue

Overview

HTML
<!--
General Design description
 -->

ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.

Key Features

HTML
<!--
Add Basic Key Features of the design (should be tested)
 -->
Excerpt
  • PetaLinux
  • SD
  • ETH
  • USB
  • I2C
  • RTC
  • FMeter
  • SI5338 Initialisation with FSBL

Revision History

HTML
<!--
- Add changes from design
- Export PDF to download, if vivado revision is changed!
  -->

...

  • fixed SD WP

...

  • initial release

Release Notes and Know Issues

HTML
<!--
- add known Design issues and general Notes for the current revision
 -->

...

Requirements

Software

HTML
<!--
Add needed external Software
   -->

...

Hardware

HTML
<!--
Hardware Support
   -->

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

...

  • A,L: 128MB Flash
  • 3,L: Lower Connector profile

...

TE0820-02-2CG-1E
TE0820-02-2CG-1EA

...

  • A: 128MB Flash

...

  • A,L: 128MB Flash
  • 3,L:  Lower Connector profile

...

  • A: 128MB Flash

Design supports following carriers:

...

...

...

...

...

  • Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
  • No SD Slot available, pins goes to Pin Header
  • For TEBA0841 REV01, please contact TE support

Additional HW Requirements:

...

Content

HTML
<!--
Remove unused content
  -->

For general structure and of the reference design, see Project Delivery

Design Sources

...

Additional Sources

...

Prebuilt

HTML
<!-- 

<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
-->

...

File

...

File-Extension

...

Description

...

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

HTML
<!--
Add correct path:https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0803/Reference_Design/2017.1/Starterkit
  -->

Reference Design is available on:

Design Flow

HTML
<!--
Basic Design Steps
Add/ Remove project specific 
  -->
Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

 

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image Removed
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (bl31.elf, uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
        Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
  7. Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

Programming

HTML
<!--
Description of Block Design, Constrains...
BD Pictures from Export...
  -->
Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.

QSPI

HTML
<!--
Example:
Connect JTAG and power on PCB
(if not done) Select 
correct device and Xilinx install path on "design_basic_settings.cmd" 
and create Vivado project with "vivado_create_project_guimode.cmd" or 
open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)

   -->

Use this description for CPLD Firmware with QSPI Boot selectable.

  1. Set Boot Mode to JTAG (See Carrier and TE0820 CPLD description)
  2. Connect JTAG
  3. Power ON PCB
  4. Program Flash
    1. Open Vivadi HW-Manager (use Auto Connect)
    2. Right Click on FPGA Device (xczu...) and "Add Configuration Memory Device"
    3. Select "mt25qu256-qspi-x8-dual_parallel"
    4. On "Program Configuration Memory Device":
      1. Set Configuration file: "prebuilt\boot_images\<short name>\u-boot\BOOT.bin"
      2. Set Zynq FSBL: "prebuilt\software\<short name>\zynqmp_fsbl.elf"
      3. Press OK
    5. Note: Other possible ways, see Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
               Do not use Trenz Script for Programming at the moment. Dual Parallel Flash Scripts support is not implemented.
  5. Copy image.ub on SD-Card.
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  6. Power OFF PCB
  7. Set Boot Mode to QSPI
    • Depends on Carrier, see carrier TRM.

SD

Use this description for CPLD Firmware with SD Boot selectable.

  1. Copy image.ub and Boot.bin on SD-Card.
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card or QSPI as Boot Mode (Depends on used programming variant)
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. ZynqMP Boot ROM loadsPMU Firmware and  FSBL from SD into OCM, 2. FSBL loads ATF(bl31.elf)and U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 0 Bus type: i2cdetect -y -r 0
    2. RTC check: dmesg | grep rtc
    3. ETH0 works with udhcpc
    4. USB type  "lsusb" or connect USB2.0 device

Vivado HW Manager

SI5338_CLK0 Counter: 

  1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
    1. Set radix from VIO signals to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz

SI5338 CLK is configured to  200MHz by default.

PHY LEDS

CPLD Firmware:

 Image Removed

System Design - Vivado

HTML
<!--
Description of Block Design, Constrains...
BD Pictures from Export...
  -->

Block Design

Image Removed

PS Interfaces

Activated interfaces:

...

Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design

Design specific constrain

Code Block
languageruby
title_i_io.xdc
set_property PACKAGE_PIN K9 [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property DIFF_TERM TRUE [get_ports {SI5338_CLK0_D_clk_p[0]}]

set_property PACKAGE_PIN H1 [get_ports {x0_phy_led[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x0_phy_led[0]}]
set_property PACKAGE_PIN J1 [get_ports {x1_firmware[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x1_firmware[0]}]

Software Design - SDK/HSI

HTML
<!--
optional chapter
separate sections for different apps
  -->

For SDK project creation, follow instructions from:

SDK Projects

Application

FSBL

TE modified 2017.2 FSBL

Changes:

  • Si5338 Configuration, ETH+OTG Reset over GPIO see xfsbl_board.c and xfsbl_board.h
  • Add register_map.h, si5338.c, si5338.h

PMU

Xilinx default PMU firmware.

Hello World

Xilinx default Hello world example. Note: Hello World output appears only on time on power up. 

U-Boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

HTML
<!--
optional chapter
Add "No changes." or "Activate: -->List"
   -->

For PetaLinux installation and  project creation, follow instructions from:

Config

No changes.

U-Boot

  • Change platform-top.h
Code Block
languagejs
#include <configs/platform-auto.h>

/* Bugfix to select SD1 instead of eMMC(SD0) */
#define CONFIG_EXTRA_ENV_SETTINGS \
    SERIAL_MULTI \ 
    CONSOLE_ARG \ 
    PSSERIAL0 \ 
    "nc=setenv stdout nc;setenv stdin nc;\0" \ 
    "ethaddr=00:0a:35:00:22:01\0" \
    "importbootenv=echo \"Importing environment from SD ...\"; " \ 
        "env import -t ${loadbootenv_addr} $filesize\0" \ 
    "loadbootenv=load mmc $sdbootdev:$partid ${loadbootenv_addr} ${bootenv}\0" \ 
    "sd_uEnvtxt_existence_test=test -e mmc $sdbootdev:$partid /uEnv.txt\0" \ 
    "uenvboot=" \ 
    "if run sd_uEnvtxt_existence_test; then" \ 
        "run loadbootenv" \ 
        "echo Loaded environment from ${bootenv};" \ 
        "run importbootenv; \0" \ 
    "sdboot=echo boot Petalinux; run uenvboot ; mmcinfo && fatload mmc 1 ${netstart} ${kernel_img} && bootm \0" \ 
    "autoload=no\0" \ 
    "clobstart=0x10000000\0" \ 
    "netstart=0x10000000\0" \ 
    "dtbnetstart=0x11800000\0" \ 
    "loadaddr=0x10000000\0" \ 
    "boot_img=BOOT.BIN\0" \ 
    "load_boot=tftpboot ${clobstart} ${boot_img}\0" \ 
    "update_boot=setenv img boot; setenv psize ${bootsize}; setenv installcmd \"install_boot\"; run load_boot ${installcmd}; setenv img; setenv psize; setenv installcmd\0" \ 
    "install_boot=mmcinfo && fatwrite mmc 1 ${clobstart} ${boot_img} ${filesize}\0" \ 
    "bootenvsize=0x40000\0" \ 
    "bootenvstart=0x100000\0" \ 
    "eraseenv=sf probe 0 && sf erase ${bootenvstart} ${bootenvsize}\0" \ 
    "jffs2_img=rootfs.jffs2\0" \ 
    "load_jffs2=tftpboot ${clobstart} ${jffs2_img}\0" \ 
    "update_jffs2=setenv img jffs2; setenv psize ${jffs2size}; setenv installcmd \"install_jffs2\"; run load_jffs2 test_img; setenv img; setenv psize; setenv installcmd\0" \ 
    "sd_update_jffs2=echo Updating jffs2 from SD; mmcinfo && fatload mmc 1:1 ${clobstart} ${jffs2_img} && run install_jffs2\0" \ 
    "install_jffs2=sf probe 0 && sf erase ${jffs2start} ${jffs2size} && " \ 
        "sf write ${clobstart} ${jffs2start} ${filesize}\0" \ 
    "kernel_img=image.ub\0" \ 
    "load_kernel=tftpboot ${clobstart} ${kernel_img}\0" \ 
    "update_kernel=setenv img kernel; setenv psize ${kernelsize}; setenv installcmd \"install_kernel\"; run load_kernel ${installcmd}; setenv img; setenv psize; setenv installcmd\0" \ 
    "install_kernel=mmcinfo && fatwrite mmc 1 ${clobstart} ${kernel_img} ${filesize}\0" \ 
    "cp_kernel2ram=mmcinfo && fatload mmc 1 ${netstart} ${kernel_img}\0" \ 
    "dtb_img=system.dtb\0" \ 
    "load_dtb=tftpboot ${clobstart} ${dtb_img}\0" \ 
    "update_dtb=setenv img dtb; setenv psize ${dtbsize}; setenv installcmd \"install_dtb\"; run load_dtb test_img; setenv img; setenv psize; setenv installcmd\0" \ 
    "sd_update_dtb=echo Updating dtb from SD; mmcinfo && fatload mmc 1:1 ${clobstart} ${dtb_img} && run install_dtb\0" \ 
    "fault=echo ${img} image size is greater than allocated place - partition ${img} is NOT UPDATED\0" \ 
    "test_crc=if imi ${clobstart}; then run test_img; else echo ${img} Bad CRC - ${img} is NOT UPDATED; fi\0" \ 
    "test_img=setenv var \"if test ${filesize} -gt ${psize}\\; then run fault\\; else run ${installcmd}\\; fi\"; run var; setenv var\0" \ 
    "netboot=tftpboot ${netstart} ${kernel_img} && bootm\0" \ 
    "default_bootcmd=run cp_kernel2ram && bootm ${netstart}\0" \ 
""

Device Tree

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
};


/* SDIO */

&sdhci1 {
  disable-wp;
};

/* ETH PHY */
&gem3 {

    status = "okay";
  ethernet_phy0: ethernet-phy@0 {
        compatible = "marvell,88e1510";
        device_type = "ethernet-phy";
            reg = <1>;
    };
};


/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "n25q256a";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};

/* DMA not used: Reduce error messages on linux.*/

&lpd_dma_chan1 {
    status = "disabled";
};
&lpd_dma_chan2 {
    status = "disabled";
};
&lpd_dma_chan3 {
    status = "disabled";
};
&lpd_dma_chan4 {
    status = "disabled";
};
&lpd_dma_chan5 {
    status = "disabled";
};
&lpd_dma_chan6 {
    status = "disabled";
};
&lpd_dma_chan7 {
    status = "disabled";
};
&lpd_dma_chan8 {
    status = "disabled";
};

Kernel

No changes.

Rootfs

Activate:

  • i2c-tools

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

HTML
<!--
Add Description for other Software, for example SI CLK Builder ...
 -->

SI5338

Download  ClockBuilder Desktop for SI5338

  1. Install and start ClockBuilder
  2. Select SI5338
  3. Options → Open register map file
    Note: File location <design name>/misc/Si5338/RegisterMap.txt
  4. Modify settings
  5. Options → save C code header files
  6. Replace Header files from FSBL template with generated file

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

HTML
<!--
Generate new entry:
1:add new row below first
2:Copy Page Information Macro(date+user) Preview, Page Information Macro Preview
3.Update Metadate =Page Information Macro Preview+1
  -->

...

 

...

  • Add Variants with 128MB Flash
2017-11-13v.16John Hartfiel
  • Update Carrier sections
2017-11-06v.15John Hartfiel
  • Typo corrected
2017-10-23v.13John Hartfiel
  • Update Key Features section
  • Style Update Additional Software section
2017-10-19
v.9
John Hartfiel
  • Release 2017.2
2017-09-11v.1

Page info
created-user
created-user

Initial release

...


All

Page info
modified-users
modified-users

...



Legal Notices

Include Page
IN:Legal Notices
IN:Legal Notices

...



Scroll Only


HTML
<style>
.wiki-content .columnLayout .cell.aside {
width: 0%;
}</style>



Scroll pdf ignore


Custom_fix_page_content

Table of contents

Table of Contents
outlinetrue