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Table of Contents

Table of Contents

...

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Image RemovedImage Added

Figure 1: TEB0729-02 03 block diagram.

Main Components

 

Figure 2: TEB0729-02 03 main components (picture shows PCB REV02).

  1. 5V barrel jack, J12
  2. RJ-45 Gigabit Ethernet MegJack, J3
  3. RJ-45 10/100-BaseT Ethernet MegJack, J4
  4. RJ-45 10/100-BaseT Ethernet MegJack, J5
  5. VG96 connector placeholder, J9
  6. XMOD (TE0790) header, JB3
  7. 2-pin header for VBAT-IN supply-voltage, J2
  8. 2x6 pin header for setting VCCIO_33, J6
  9. 2x6 pin header for setting VCCIO_13, J7
  10. MicroSD Card socket, J1
  11. Red LED, D1
  12. Push Button, S1
  13. Micro USB2.0 B Receptacle (optional USB2.0 Type A socket)
  14. VG96 connector placeholder, J8
  15. B2B Connector, JB1
  16. B2B Connector, JB2
  17. 4-bit DIP-switch, S2

...

The TEB0729 Carrier Board's Board-to-Board Connectors (B2B) have the same pin-assignment as the mounted Zynq SoM due to its hermaphroditic structure. By this connectors, the MIO- and PL-IO-bank's pins and further interfaces of the Zynq SoM can be accessed. A large quantity of these I/O's are also usable as  as LVDS-pairs. The connectors provide also VCCIO voltages to operate the I/O's properly.

Following table gives a summary of the available I/O's, interfaces and LVDS-pairs of the B2B connectors JB1 and JB2:

6
B2B ConnectorInterfacesCount of IO'sInterfacesNotes
JB1User IO24 single endedUser IO-
48 single ended or 24 differentialUser IO-
JB2

User IO

54 single ended

User IO

-
10 single ended or 5 differentialUser IO--
I²C2I²C-
7SD IO7-
UART2UART-
USB2.06-
142x 10/100-BaseT Ethernet12-
14GbE MDI and SGMII14-
JTAG4JTAG-

Table 2: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.

...

On the VG96 connector J9 are signals assigned to control the SoM and the interfaces of the SoM's Zynq chip device and of its on-module peripherals:

Following table gives a summary of the pin-assignment, available interfaces and functional IO's of the VG96 connectors J8 and J9:

5
VG96 ConnectorControl Signals and InterfacesCount of PL IO'sCount of LVDS-pairsSoM Control Signals and InterfacesNotes
J87224--
Notes
J8User IO24 single ended-
48 single ended or 24 differential-
J9

User IO

54 single ended-
10 single ended or 5 differential-J964
'NRST_IN' , (pin J9-A29Drive to ground (Push Button S1, JB3-11 (G) on XMOD header) to reset the SoM. 2)'NRST_OUT', ), 'RST_STATUS' (pin J9-B30Incoming reset signal from SoM's watchdog (implemented on SoM's SC CPLD). 2))2

These pins are dedicated to the specific Reset-functionality of the TE0729 SoM.

'BOARD_STAT' , (pin J9-B32)1-Frequently flipping signal indicating running SoM. Routed also to XMOD Header, pin JB3-9 (E).
'BOOT_MODE1' , (pin J9-C31Bootmode pin 1, use in conjunction with Bootmode pin 2.), 'BOOT_MODE2' , (pin J9-C32)Bootmode pin 2, use in conjunction with Bootmode pin 1.2Binary bootmode code of SoM, also connected to DIP S2
I²C2I²C, pins J9-A30, J9-A31I²C1 interface of module.
GbE SGMII, pins J9-A16, J9-A17, J9-A19 J9-A204SGMII interface of on-module GbE PHY.
VG96 ConnectorCount of IO'sControl Signals and InterfacesNotesJ824 single endedUser IO-48 single ended or 24 differentialUser IO-J954 single ended

User IO

-10 single ended or 5 differentialUser IO-'NRST_IN', pin J9-A29I²C-'NRST_OUT', pin J9-B30SD IO-'BOARD_STAT', pin J9-B32UART-'BOOT_MODE1', pin J9-C31USB2.0-'BOOT_MODE2', pin J9-C32I²C, pins J9-A30, J9-A312x 10/100-BaseT Ethernet-GbE SGMIIGbE MDI and SGMII-4JTAG-

Table 3: General overview of PL I/O signals, SoM's interfaces and control signals  connected to the VG96 connectors.

HW-modification Concerning Reset-Signals

2) The pins with the schematic net names 'NRST_IN' (JB2-89) and 'NRST_OUT' (JB2-91) are swapped as part of a HW-modification to rework the Reset-signals of the Carrier-Board in conjunction with the TE0729 SoM.

Refer to the SC CPLD documentation, section "Watchdog" to get further detailed information about the Reset-functionality of the Carrier Board and SoM before and after the HW-modification and the required SC CPLD firmware revision of the TE0729 SoM for each version of the SoM.

JTAG Interface

JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JB3. With the TE0790 XMOD USB2.0 to JTAG adapter, the Zynq chip on the mounted SoM can be programed via USB2.0 interface.

...

JTAG Signal

...

B2B Connector Pin

...

Table 4: JTAG interface signals.

UART Interface

UART interface is available on B2B connector JB2. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:

...

Table 3: General overview of PL I/O signals, SoM's interfaces and control signals  connected to the VG96 connectors.

JTAG Interface

JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JB3. With the TE0790 XMOD USB2.0 to JTAG adapter, the Zynq device on the mounted SoM can be programed via USB2.0 interface.

JTAG Signal

B2B Connector Pin

XMOD Header JB3Note
TCKJB2-119JB3-4-
TDIJB2-115JB3-10-
TDOJB2-117JB3-8-
TMSJB2-113JB3-12-
JTAGSELJB2-111-Select SoM's JTAG programming mode on DIP-switch S2-1.

Table 4: JTAG interface signals.

UART Interface

UART interface is available on B2B connector JB2. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:

UART Signal Schematic NameB2BXMOD Header JB3Note
USART0_RXJB2-94JB3-7UART receive line
USART0_TXJB2-96JB3-3UART transmit line

Table 5: UART interface signals.

I²C Interface

Two I²C interfaces are provided on B2B connector JB2. I²C0 interface is connected to the Configuration EEPROMs U1 and U2 and is dedicated to these on-board peripherals. Interface I²C1 is routed to the VG96 connector J9 and is available to the user for general purposes:

I²C Signal Schematic NameB2BConnected toNote
I2C0_SDAJB2-90EEPROMs U1, U2I²C data line
I2C0_SCLJB2-92EEPROMs U1, U2I²C clock line
I2C1_SDAJB2-93J9-A30I²C data line
I2C1_SCLJB2-95J9-A31I²C clock line

Table 6: I²C interface signals.

SD IO Interface

The SD IO interface of the SoM's Zynq device (MIO-bank) is routed to the on-board MicroSD Card socket J1. By this interface, the Zynq device can be booted from an inserted MicroSD Card:

SD IO Signal Schematic NameB2BConnected toNote
ESD_DAT0JB2-108J1-7SD IO data
ESD_DAT1JB2-110J1-8SD IO data
ESD_DAT2JB2-100J1-1SD IO data
ESD_DAT3JB2-102J1-2SD IO data
ESD_CLKJB2-106J1-5SD IO clock
ESD_CMDJB2-104J1-3SD IO command
MIO0JB2-87J1-9Card Detect signal

Table 7: SD IO interface signals.

USB2.0 Interface

The TEB0729 Carrier Board is equipped with a Micro USB2.0 B (receptacle) socket J11 with board-revision TEB0729-03B, USB2.0 Type A socket is fitted on board-revision TEB0729-03A.

The differential data signals of the USB2.0 socket are routed to the B2B connector JB2, where they can be accessed by the USB2.0 transceiver of the mounted SoM. The USB2.0 connector can be used for Device mode, OTG Mode or Host Modes. For USB Host mode, the Carrier Board is additionally equipped with a power distribution switch U3 to provide the USB2.0 interface with the USB supply voltage USB-VBUS with nominal value of 5V. OTG mode is not available with USB2.0 Type A socket.

Following table gives an overview of the USB2.0 interface signals:

USB2.0

Table 5: UART interface signals.

I²C Interface

Two I²C interfaces are provided on B2B connector JB2. I²C0 interface is connected to the Configuration EEPROMs U1 and U2 and is dedicated to these on-board peripherals. Interface I²C1 is routed to the VG96 connector J9 and is available to the user for general purposes:

I²C 90
Signal Schematic NameB2BConnected toNote
I2C0OTG-D_SDAN

JB2-

EEPROMs U1, U2I²C data line
I2C0_SCLJB2-92EEPROMs U1, U2I²C clock line
I2C1_SDAJB2-93J9-A30I²C data line
I2C1_SCLJB2-95J9-A31I²C clock line

Table 6: I²C interface signals.

SD IO Interface

The SD IO interface of the SoM's Zynq chip (MIO-bank) is routed to the on-board MicroSD Card socket J1. By this interface, the Zynq chip can be booted from an inserted MicroSD Card:

...

Table 7: SD IO interface signals.

USB2.0 Interface

The TEB0729 Carrier Board is equipped with a Micro USB2.0 B (receptacle) socket J11 with board-revision TEB0729-02B, USB2.0 Type A socket is fitted on board-revision TEB0729-02A.

The differential data signals of the USB2.0 socket are routed to the B2B connector JB2, where they can be accessed by the USB2.0 transceiver of the mounted SoM. The USB2.0 connector can be used for Device mode, OTG Mode or Host Modes. For USB Host mode, the Carrier Board is additionally equipped with a power distribution switch U3 to provide the USB2.0 interface with the USB supply voltage USB-VBUS with nominal value of 5V. OTG mode is not available with USB2.0 Type A socket.

Following table gives an overview of the USB2.0 interface signals:

...

JB2-103

...

103

J11-2, (J10-2)USB2.0 data
OTG-D_PJB2-101J11-3, (J10-3)USB2.0 data
OTG-IDJB2-109J11-4Ground this pin for A-Device (host),  left floating this pin for B-Device (peripheral).
VBUS_V_ENJB2-97U3, pin 4Enable USB-VBUS.
USB-VBUSJB2-107J11-1, (J10-1)USB supply voltage in Host mode.
USB_OCJB2-48, J9-B29U3, pin 5USB-VBUS over current signal: current-limit threshold exceeded by the connected USB device in USB Host mode.

Table 8: USB2.0 interface signals and connections.

Gigabit Ethernet Interface

The TEB0729 Carrier Board is fitted with one RJ-45 Gigabit Ethernet Magnetic jack J3. The MegJack has two integrated LEDs (both green), its signals are routed as MDI (Media Dependent Interface) to the B2B connector JB2, where they can be accessed by the GbE PHY transceiver of the mounted SoM:

GbE PHY Signal Schematic NameB2BConnected toNotes
PHY_MDI0_P

JB2-84

J3-2 -
PHY_MDI0_NJB2-82J3-3-
PHY_MDI1_PJB2-78J3-4-
PHY_MDI1_NJB2-76J3-5-
PHY_MDI2_PJB2-72J3-6-
PHY_MDI2_NJB2-70J3-7-
PHY_MDI3_PJB2-66J3-8-
PHY_MDI3_NJB2-64J3-9-
PHY_LED0JB2-59Green MegJack J3 LED-
PHY_LED1JB2-57Green MegJack J3 LED-

Table 9: GbE interface signals and connections.


For the same GbE transceiver PHY on the mounted SoM, on the Carrier Board is also SGMII (Serial Gigabit Media Independent Interface) available. The SGMII pins are available on VG96 connector J9:

GbE PHY Signal Schematic NameB2BConnected toNotes
SIN_P

JB2-52

J9-A16 -
SIN_NJB2-54J9-A17-
SOUT_PJB2-58J9-A19-
SOUT_NJB2-60J9-A20-

Table 10: GbE SGMII signals and connections.

10/100-BaseT

Table 8: USB2.0 interface signals and connections.

...

Ethernet Interface

The TEB0729 Carrier Board is also fitted with one two additional RJ-45 Gigabit Ethernet Magnetic jack J3. The MegJack has two integrated LEDs (both green), its signals are routed as MDI (Media Dependent Interface) MegJacks providing 10/100-BaseT Ethernet interfaces. This interfaces are routed to the B2B connector JB2, where they can be accessed by the GbE PHY transceiver of the mounted SoM:

PHY_MDI1
10/100-BaseT GbE PHY Signal Schematic NameB2BConnected toNotes
PHY_MDI0_P

JB2-84

J3-2 -
PHY_MDI0_NJB2-82J3-3-
toNotes
ETH1_RX_P

JB2-

78

26

J3J4-43 -
PHYETH1_MDI1RX_NJB2-7628J3J4-56-
PHYETH1_MDI2TX_PJB2-7220J3J4-61-
PHYETH1_MDI2TX_NJB2-7022J3J4-72-
PHYETH1_MDI3_PLED0JB2-66J3-834Yellow MegJack J4 LED-
PHYETH1_MDI3_NLED1JB2-64J3-932Green MegJack J4 LED-




PHYETH2_RX_LED0PJB2-598J5-3Green MegJack J3 LED-
PHYETH2_RX_LED1NJB2-57Green MegJack J3 LED-

Table 9: GbE interface signals and connections.

...

10J5-6-
ETH2_TX_PJB2-2J5-1-
ETH2_TX_NJB2-4J5-2-
ETH2_LED0JB2-16Yellow MegJack J5 LED-
ETH2_LED1JB2-14Green MegJack J5 LED-

Table 11: 10/100-BaseT Ethernet interfaces signals and connections.

XMOD FTDI JTAG-Adapter Header

The JTAG interface of the mounted SoM can be accessed via header JB3, which has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment. So in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM can be programmed via USB interface. The TE0790 board provides also an UART interface to the Zynq SoM which can be accessed by the USB2.0 interface of the adapter-board while the signals between these serial interfaces will be converted. The adapter-board offers also two GPIO's, one with an indication LED (pin JB3-9 (E)) and another one with a low-active push button (pin JB3-11 (G)).

Following table describes the signals and interfaces of the XMOD header JB3:

JB3 pinSignal Schematic Net NameB2BNote
C (pin 4)TCKJB2-119-
D (pin 8)TDOJB2-117-
F (pin 10)TDIJB2-115-
H (pin 12)TMSJB2-113-
A (pin 3)USART0_TXJB2-96-
B (pin 7)USART0_RXJB2-94-
E (pin 9)BOARD_STATJB2-112also connected to VG96 connector pin J9-B32
G (pin 11) 2)NRST_INJB2-89

also connected to VG96 connector pin J9-A29

Table 12: XMOD header signals and connections.  2) Pin connected to push button S1 on XMOD FTDI JTAG Adapter

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the Carrier Board. Set the DIP-switch with the setting:

XMOD DIP-switchesPosition
Switch 1ON
Switch 2OFF
Switch 3OFF
Switch 4ON

Table 13: XMOD adapter board DIP-switch positions for voltage configuration.


Note

Use Xilinx compatible TE0790 adapter board (designation TE0790-xx with out 'L') to program the Zynq device.

The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download.

On-board Peripherals

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Configuration EEPROM

The TEB0729 Carrier Board is equipped with two Configuration EEPROMs U1 and U2 from Microchip.

  • U1: Microchip 24LC128: 128 KBit memory density (8 pages a 16 KBit), 400 KHz max. clock frequency
    • I²C-Address: 1010 101
  • U2: Microchip 24AA025E48T: 2 KBit memory density (2 block of 128 x 8-bit words), 400 KHz max. clock frequency
    • I²C-Address: 1010 011

The Configuration EEPROMs are connected to the I²C0 interface of the Zynq's MIO-bank via B2B connector JB2.

4-bit DIP-switch

Table below describes DIP-switch S2 settings for configuration of the mounted SoM:

DIP-switches S2Signal Schematic Net NameFunctionNote
S2-1JTAGSEL

Select Zynq device or SC CPLD programming of mounted SoM:

OFF:  Zynq device in JTAG chain
ON:    CPLD in JTAG chain

Refer also to the TE0729 SC CPLD documentation for detailed information about JTAG update
S2-2BOOT_MODE1Select first bit of boot mode codeRefer to TE0729 TRM and SC CPLD documentation for detailed information about boot modes
S2-3BOOT_MODE2Select second bit boot mode code
S2-4xxnot used

Table 14: DIP-Switch S2 SoM configuration settings


Boot ModeS2-2S2-3
JTAGONON
SDOFFOFF
QSPIONOFF

Table 15Boot Modes configuration via DIP-switch S2 with default TE0729 CPLD Firmware

VCCIO Selection Jumper

The Carrier Board VCCIO for the PL IO-banks of the mounted SoM are selectable by the jumpers J6 and J7.

Following table describes how to configure the VCCIO of the SoM's banks with jumpers:

VCCIO
vs. Voltage Levels
VCCIO_13VCCIO_33Note
1.8VJ7:pins 1-2J6: pins 1-2-
2.5VJ7: pins 3-4J6: pins 3-4-
3.3VJ7: pins 5-6J6: pins 5-6-

Table 16: VCCIO jumper settings.

RTC Buffer Voltage Supply Header

The buffer voltage of the SoM's RTC can be supplied through the header J2. Refer to the SoM's TRM for recommended voltage range and absolute maximum ratings.

Push Button

The Carrier Board's push button S1 is connected to the 'NRST_IN' signal, the function of the button is to trigger a reset of the mounted SoM by driving the reset-signal 'NRST_IN' to ground.

On-board LEDs

LED ColorConnected toDescription and Notes
D1Red'MIO9', pin JB2- 88user LED

Table 17: On-board LEDs.

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of the Carrier Board depends mainly on the mounted SoM's FPGA design running on the Zynq device.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power InputTypical Current
5VINTBD*

Table 18: Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended.

Warning
To avoid any damage to the module, check for stabilized on-board voltages and VCCIO's before put voltages on PL I/O-banks and interfaces. All I/Os should be tri-stated during power-on sequence.

Power Distribution Dependencies

The Carrier Board needs one single power supply voltage with a nominal value of 5V. Following diagram shows the distribution of the input voltage '5VIN' to the on-board components on the mounted SoM:


Image Added

Figure 3: Board power distribution diagram.

Power Rails

The voltage direction of the power rails is directed at on-board connectors' view:

Module Connector (B2B) DesignatorVCC / VCCIODirectionPinsNotes
JB1

VIN33

Out

1, 2, 3, 4, 5, 6

3.3V module supply voltage
VCCIO_13Out101, 102PL IO-bank VCCIO
VCCIO_33Out29, 30PL IO-bank VCCIO
3.3VIn65, 66voltage output from module
JB2

1.8V

In

49

voltage output from module
2.5VIn13voltage output from module
USB-VBUSOut107USB Host supply voltage
VBAT_INOut118RTC buffer voltage

Table 19: Power pin description of B2B Module Connector.


Jumper / Header DesignatorVCC / VCCIODirectionPinsNotes
J6VCCIO_33In2, 4, 6-
1.8VOut5-
2.5VOut3-
3.3VOut1-
J7

VCCIO_13

In2, 4, 6-
1.8VOut5-
2.5VOUt3-
3.3VOut1-

Table 20: Power Pin description of VCCIO selection jumper pin header.


Main Power Jack and Pins

...

JB2-52

...

Table 10: GbE SGMII signals and connections.

10/100-BaseT Ethernet Interface

The TEB0729 Carrier Board is also fitted with two additional RJ-45 MegJacks providing 10/100-BaseT Ethernet interfaces. This interfaces are routed to the B2B connector JB2

...

JB2-26

...

Table 11: 10/100-BaseT Ethernet interfaces signals and connections.

XMOD FTDI JTAG-Adapter Header

The JTAG interface of the mounted SoM can be accessed via header JB3, which has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment. So in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM can be programmed via USB interface. The TE0790 board provides also an UART interface to the Zynq SoM which can be accessed by the USB2.0 interface of the adapter-board while the signals between these serial interfaces will be converted. The adapter-board offers also two GPIO's, one with an indication LED (pin JB3-9 (E)) and another one with a low-active push button (pin JB3-11 (G)).

Following table describes the signals and interfaces of the XMOD header JB3:

...

Table 12: XMOD header signals and connections.  3) Swapped at HW-Modification with signal 'NRST_OUT' in board-revision 2

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the Carrier Board. Set the DIP-switch with the setting:

...

Table 13: XMOD adapter board DIP-switch positions for voltage configuration.

On-board Peripherals

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Configuration EEPROM

The TEB0729 Carrier Board is equipped with two Configuration EEPROMs U1 and U2 from Microchip.

  • U1: Microchip 24LC128: 128 KBit memory density (8 pages a 16 KBit), 400 KHz max. clock frequency
    • I²C-Address: 1010 101
  • U2: Microchip 24AA025E48T: 2 KBit memory density (2 block of 128 x 8-bit words), 400 KHz max. clock frequency
    • I²C-Address: 1010 011

The Configuration EEPROMs are connected to the I²C0 interface of the Zynq's MIO-bank via B2B connector JB2.

4-bit DIP-switch

Table below describes DIP-switch S2 settings for configuration of the mounted SoM:

...

Select Zynq chip or SC CPLD programming of mounted SoM:

OFF:  Zynq chip programming.
ON:    SC CPLD programming

...

Table 14: DIP-Switch S2 SoM configuration settings.

TE0729 Bootmodes

If TE0729 is mounted, following bootmodes can be configured by setting the DIP-switches S2-2 and S2-3:

...

Table 15: Bootmode configuration via DIP-switch S2.

The selected bootmode via DIP-switch S2 depends also on the current configured SC CPLD firmware on the mounted SoM and may vary.

VCCIO Setting Jumper

The Carrier Board VCCIO for the PL IO-banks of the mounted SoM are selectable by the jumpers J6 and J7.

Following table describes how to configure the VCCIO of the SoM's banks with jumpers:

...

Table 16: VCCIO jumper settings.

RTC Buffer Voltage Supply Header

The buffer voltage of the SoM's RTC can be supplied through the header J2. Refer to the SoM's TRM for recommended voltage range and absolute maximum ratings.

Push Button

The Carrier Board's push button S1 is connected to the 'NRST_IN' signal, the function of the button is to trigger a reset of the mounted SoM by driving the reset-signal 'NRST_IN' to ground.

On-board LEDs

...

Table 17: On-board LEDs.

Power and Power-On Sequence

HTML
<!--
If power sequencing and distribution is not so much, you can join both sub sections together
  -->

Power Consumption

The maximum power consumption of the Carrier Board depends mainly on the mounted SoM's FPGA design running on the Zynq chip.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

...

Table 18: Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended.

Warning
To avoid any damage to the module, check for stabilized on-board voltages and VCCIO's before put voltages on PL I/O-banks and interfaces. All I/Os should be tri-stated during power-on sequence.

Power Distribution Dependencies

The Carrier Board needs one single power supply voltage with a nominal value of 5V. Following diagram shows the distribution of the input voltage '5VIN' to the on-board components on the mounted SoM:

Image Removed

Figure 3: Board power distribution diagram.

Power Rails

JB1
Module Connector (B2B) DesignatorVCC / VCCIODirectionPinsNotes
J12VIN335VINOutIn

Pin 1, 2, 3, 4, 5, 6

3.3V module supply voltage
VCCIO_13OutPin 101, 102PL IO-bank VCCIO
VCCIO_33OutPin 29, 30PL IO-bank VCCIO
3.3VInPin 65, 66voltage output from module
JB2

1.8V

In

Pin 49

voltage output from module
2.5VInPin 13voltage output from module
USB-VBUSOutPin 107USB Host supply voltage
VBAT_INOutPin 118RTC buffer voltage

Table 19: Power pin description of B2B Module Connector.

1

-
J95VINIn / OutA1, A2also usable as '5VIN' power supply to the Carrier Board as alternative to J12
J2VBAT_INIn1Attention: Pin 2 connected to ground. VBAT_IN voltage on this pin cause short-circuit.

Table 21: Main Power jack and pins description.


Peripheral Socket DesignatorVCC / VCCIODirectionPinsNotes
J10 / J11USB-VBUSIn / Out1Direction depends on USB2.0 mode
J1VIN33Out4MikroSD Card socket VDD

Table 22: Power pin description of peripheral connector.


-In1-J7
XMOD Jumper / Header DesignatorVCC / VCCIODirectionPinsNotes
J6VCCIO_33OutPin 2, 4, 6-
1.8VIn5-
2.5VIn3JB33.3V-5not connected
VIO

VCCIO_13

OutPin 2, 4, 6-
1.8VIn5-
2.5VIn3-
3.3VIn1-

Table 20: Power Pin description of VCCIO selection jumper pin header.

...

-

...

6connected to VIN33

Table 23: Power pin description of XMOD/JTAG Connector.

Board to Board Connectors

The TE0729 module has two 120-pin double-row REF-189019-02 connectors on the bottom side which are compatible with Samtec BSE-060-01-L-D-A connectors. Mating connectors on the baseboard are REF-189019-01, which are compatible with Samtec BTE-060-01-L-D-A connectors.

Order
number

REF NumberSamtec NumberTypeMated HeightData sheetComment
-REF-189019-02BTE-060-01-L-D-A-K-TRModule connector5 mmhttp://suddendocs.samtec.com/catalog_english/bte.pdfStandard connector
used on module
26663REF-189019-01BSE-060-01-L-D-A-TRBaseboard connector5 mmhttp://suddendocs.samtec.com/catalog_english/bse.pdfStandard connector
used on board

Table 24: B2B Connectors.


Connector SpecificationsValue
Insulator materialLiquid crystal polymer
Stacking height5 mm
Contact materialPhosphor-bronze
PlatingAu or Sn over 50 μ" (1.27 μm) Ni
Current rating2 A per pin (1 pin powered per row)
Operating temperature range-55 °C to +125 °C
Voltage rating225 VAC with 5 mm stack height
Max cycles100
RoHS compliantYes

Table 25: B2B Connector specifications.

Table 21: Main Power jack and pins description.

...

Table 22: Power pin description of peripheral connector.

...

Table 23: Power pin description of XMOD/JTAG Connector.

Board to Board Connectors

Include PageIN:Samtec LSHMIN:Samtec LSHM

Variants Currently In Production

 Module Variant

Operating Temperature

USB SocketTemperature Range
TEB0729-0203-A-40°C to +125°CUSB2.0 Type A socket fittedIndustrial
TEB0729-0203-B-40°C to +125°CMicro USB2.0 B socket fittedIndustrial

Table 2426: Module Board variants.

Technical Specifications

...

Parameter

MinMax

Units

Reference Document

5VIN supply voltage

 -0.3 7

V

MP5010A, EN6347QI data sheet

Storage temperature

 -65

150

°C

-

Table 2527: Module absolute maximum ratings.

...

ParameterMinMaxUnitsReference Document
5VIN supply voltage 4.755.25 VUSB2.0 specification concerning 'VBUS' voltage
Operating temperature -40125°C-

Table 2628: Module recommended operating conditions.

...

Hardware Revision History

 -
DateRevision

Notes

PCNSchematic Change NotesDocumentation LinkNote
-

01

  • First Production Release
 -TEB0729-01

First Production Release

-02
  • Second Production Release
  • HW-Modification since 22.08.2017
  • Refer to Changes list in Schematic

    for further details in changes to REV01

-TEB0729-0102
--02Second Production Release-03
  • Rework Reset-Signals by Pin-Swap
  • Refer to Changes
Refer to Changes
  • list in Schematic
TEB0729-02HW-Modification since 22.08.2017
  • for
    further details in changes to REV02
-TEB0729-03

Table 29Table 27: Module hardware revision history.

...

Date

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd



Ali Naseri
  • update TRM to board revision 03

2017-10-27

v.14
Ali Naseri
  • initial document to board revision 02

Table 2830: Document change history.

...