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Table of Contents
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Overview
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Refer to https://wiki.trenz-electronic.de/display/PD/TE0745+TRM for online version of this manual and the rest of the available documentation. |
The Trenz Electronic TE0745 is an industrial-grade module integrating a Xilinx Zynq SoC (XC7Z-030, XC7Z-035 or XC7Z-045), 1 GByte DDR3/L SDRAM, 32 MByte SPI Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips.
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Industrial grade Xilinx Zynq SoC (XCZ7030, XC7Z035, XC7Z045)
- Dual-core ARM Cortex-A9 MPCore™ with CoreSight™
- 200 250 FPGA PL I/Os (96 120 LVDS pairs possible)
- 14 17 PS MIOs on B2B connector available
- 16-bit wide 1GB DDR3L SDRAM
- 32 MByte QSPI Flash memory
- 4 or 8 GTX transceiver lanes (XC7Z030 variant has 4)
- 10/100/1000 Mbps Gigabit Ethernet transceiver PHY
- EEPROM for storing Ethernet MAC Address
- Hi-speed USB 2.0 ULPI transceiver with full OTG support
- Programmable quad clock generator
- Temperature compensated RTC (real-time clock)
- Plug-on module with 3 × 160-pin high-speed hermaphroditic strips
- On-board high-efficiency DC-DC converters
- System management
- eFUSE bit-stream encryption
- AES bit-stream encryption
- User LED
- Evenly-spread supply pins for good signal integrity
- Rugged for shock and high vibration
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Storage Device Name | Content | Notes |
|---|---|---|
24AA025E48 EEPROM | User content, not programmed | Valid MAC Address from manufacturer. |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor. |
SPI Flash Quad Enable bit | Programmed | - |
SPI Flash main array | Demo design | - |
eFUSE USER | Not programmed | - |
eFUSE Security | Not programmed | - |
| Si5338 OTP NVM | Default settings pre programmed | OTP not re-programmable after delivery from factory |
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The configuration of the I/O's MIO0, MIO12 ... MIO15 and MIO40 ... MIO51 are depending on the base-board peripherals connected to these pins.
MGT Lanes
The MGT bank signals of the SoC are routed to the B2B connectors J1 and J3. There are 8 high-speed data lanes (Xilinx GTX transceivers) available composed as differential signaling pairs for both directions (RX/TX). On B2B connector J3 there are also clock input pins for MGT transceivers.
Following MGT lanes are available on the B2B connectors:
MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pair, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:
| Bank | Type | Bank | Type | Lane Count | B2B Connector | Schematic Names / Connector Pins | MGT Bank's Reference Clock Inputs |
|---|---|---|---|---|---|---|---|
111 not available at XC7Z030 Zynq SoC | GTX | 4 | J1 | MGT_RX4_P, MGT_RX4_N, pins J1-23, J1-21 MGT_RX5_P, MGT_RX5_N, pins J1-17, J1-15 MGT_RX6_P, MGT_RX6_N, pins J1-11, J1-9 MGT_RX7_P, MGT_RX7_N, pins J1-3, J1-5 | 1 Reference clock MGT_CLK3 from programmable 1 Reference clock MGT_CLK2 from B2B connector J3 | ||
| 112 | GTX | 4 | J3 | MGT_RX3_P, MGT_RX3_N, pins J3-68, J3-70 MGT_RX2_P, MGT_RX2_N, pins J3-62, J3-64 MGT_RX1_P, MGT_RX1_N, pins J3-56, J3-58 MGT_RX0_P, MGT_RX0_N, pins J3-50, J3-52 | 1 Reference clock MGT_CLK1 from programmable 1 Reference clock MGT_CLK0 from B2B connector J3 |
Table 3: SoC's MGT lanes connections to the B2B connectors
| Lane | Bank | Type | Signal Name | B2B Pin | FPGA Pin |
|---|---|---|---|---|---|
| 0 | 112 | GTX |
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| 1 | 112 | GTX |
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| 2 | 112 | GTX |
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| 3 | 112 | GTX |
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| 4 | 111 | GTX |
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| 5 | 111 | GTX |
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| 6 | 111 | GTX |
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| 7 | 111 | GTX |
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JTAG Interface
JTAG access is provided through the SoC's PS configuration bank 0 and available on B2B connector J1.
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Overview
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