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The configuration of the I/O's MIO0, MIO12 ... MIO15 and MIO40 ... MIO51 are depending on the base-board peripherals connected to these pins.
MGT Lanes
Following MGT lanes are available on the B2B connectors:
MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pair, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:
| Lane | Bank | TypeLane | CountSignal Name | B2B Connector | Schematic Names / Connector Pins | MGT Bank's Reference Clock Inputs |
|---|---|---|---|---|---|---|
111 not available at XC7Z030 Zynq SoC | GTX | 4 | J1 | MGT_RX4_P, MGT_RX4_N, pins J1-23, J1-21 MGT_RX5_P, MGT_RX5_N, pins J1-17, J1-15 MGT_RX6_P, MGT_RX6_N, pins J1-11, J1-9 MGT_RX7_P, MGT_RX7_N, pins J1-3, J1-5 | 1 Reference clock MGT_CLK3 from programmable 1 Reference clock MGT_CLK2 from B2B connector J3 | |
| 112 | GTX | 4 | J3 | MGT_RX3_P, MGT_RX3_N, pins J3-68, J3-70 MGT_RX2_P, MGT_RX2_N, pins J3-62, J3-64 MGT_RX1_P, MGT_RX1_N, pins J3-56, J3-58 MGT_RX0_P, MGT_RX0_N, pins J3-50, J3-52 | 1 Reference clock MGT_CLK1 from programmable 1 Reference clock MGT_CLK0 from B2B connector J3 |
Table 3: SoC's MGT lanes connections to the B2B connectors
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- MGT_RX0_P
- MGT_RX0_N
- MGT_TX0_P
- MGT_TX0_N
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- J1-8
- J1-10
- J1-7
- J1-9
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- MGTHRXP0_225, Y2
- MGTHRXN0_225, Y1
- MGTHTXP0_225, AA4
- MGTHTXN0_225, AA3
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- MGT_RX1_P
- MGT_RX1_N
- MGT_TX1_P
- MGT_TX1_N
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- J1-14
- J1-16
- J1-13
- J1-15
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- MGTHRXP1_225, V2
- MGTHRXN1_225, V1
- MGTHTXP1_225, W4
- MGTHTXN1_225, W3
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- MGT_RX2_P
- MGT_RX2_N
- MGT_TX2_P
- MGT_TX2_N
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- MGT_RX3_P
- MGT_RX3_N
- MGT_TX3_P
- MGT_TX3_N
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- MGT_RX4_P
- MGT_RX4_N
- MGT_TX4_P
- MGT_TX4_N
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- J3-14
- J3-16
- J3-13
- J3-15
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| Pin | FPGA Pin | ||||
|---|---|---|---|---|---|
| 0 | 112 | GTX |
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| 1 | 112 | GTX |
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| 2 | 112 | GTX |
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| 3 | 112 | GTX |
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| 4 | 111 | GTX |
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| 5 | 111 | GTX |
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| 6 | 111 | GTX |
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| 7 | 111 | GTX |
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Table 3: SoC's MGT lanes connections to the B2B connectors
Below are listed MGT banks reference clock sources.
| Clock signal | Bank | Source | FPGA Pin | Notes |
|---|---|---|---|---|
| MGT_CLK0_P | 112 | B2B, J3-75 | MGTREFCLK0P_112, R6 | Supplied by the carrier board. |
| MGT_CLK0_N | 112 | B2B, J3-77 | MGTREFCLK0N_112, R5 | Supplied by the carrier board. |
| MGT_CLK1_P | 112 | U16, CLK0A | MGTREFCLK1P_112, U6 | On-module Si5338A. |
| MGT_CLK1_N | 112 | U16, CLK0B | MGTREFCLK1N_112, U5 | On-module Si5338A. |
| MGT_CLK2_P | 111 | B2B, J3-81 | MGTREFCLK0P_111, W6 | Supplied by the carrier board. |
| MGT_CLK2_N | 111 | B2B, J3-83 | MGTREFCLK0N_111, W5 | Supplied by the carrier board. |
| MGT_CLK3_P | 111 | U16, CLK3A | MGTREFCLK1P_111, AA6 | On-module Si5338A. |
| MGT_CLK3_N | 111 | U16, CLK3B | MGTREFCLK1N_111, AA5 | On-module Si5338A. |
Table 4: MGT reference clock sources.
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- MGT_RX5_P
- MGT_RX5_N
- MGT_TX5_P
- MGT_TX5_N
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- J3-14
- J3-16
- J3-13
- J3-15
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- MGT_RX6_P
- MGT_RX6_N
- MGT_TX6_P
- MGT_TX6_N
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- J3-14
- J3-16
- J3-13
- J3-15
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- MGT_RX7_P
- MGT_RX7_N
- MGT_TX7_P
- MGT_TX7_N
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JTAG Interface
JTAG access is provided through the SoC's PS configuration bank 0 and available on B2B connector J1.
| JTAG Signal | B2B Connector Pin |
|---|---|
| TCK | J1-143 |
| TDI | J1-142 |
| TDO | J1-145 |
| TMS | J1-144 |
Table 45: JTAG interface signals
| Note |
|---|
| JTAG_EN pin 148 in B2B connector J1 should be kept low or grounded for normal operation! |
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