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Refer to https://wiki.trenz-electronic.de/display/PD/TE0745+TRM for online version of this manual and the rest of the available documentation.

The Trenz Electronic TE0745 is an industrial-grade module integrating a Xilinx Zynq SoC (XC7Z-030, XC7Z-035 or XC7Z-045), 1 GByte DDR3/L SDRAM, 32 MByte SPI Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips.

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Figure 1: TE0745-02 Block Diagram.

Main Components

Figure 2: TE0745-02 SoC module.

1. Xilinx Zynq XC7Z family SoC, U1
2. 256 Mbit Quad SPI Flash memory Micron N25Q256A, U12
3. Reference clock signal oscillator SiTime SiT8008BI @33.333333 MHz, U12
4. Reference clock signal oscillator SiTime SiT8008BI @25.000000 MHz, U9
5. Marvell Alaska 88E1512 Gigabit Ethernet PHY, U3
6. Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16-bit word width), U3
7. TI TPS51206 DDR3 memory termination regulator with buffered reference voltage VTTREF, U18
8. Intersil ISL12020MIRZ Real-Time-Clock, U24
9. TI TCA9517 level-shifting I²C bus repeater, U17
10. Red LED, D2
    
11. Green LED, D1
12. Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 banks a 32 MWords, 16 Bit word width), U5
13. Altera Enpirion EN63A0QI 12A DC-DC PowerSoC @1.0V (VCCINT), U4
    
14. TI TPS74401RGW LDO DC-DC regulator @1.2V (MGTAVTT), U8
15. TI TPS72018DRVR LDO DC-DC regulator @1.8V (MGTAUX), U6
16. TI TPS74401RGW LDO DC-DC regulator @1.0V (MGTAVCC), U11
17. Silicon Labs Si5338A I²C Programmable Quad Clock Generator, U13
18. Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U21
19. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J3
20. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J1
21. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J2
22. 256 Mbit Quad SPI Flash memory (Micron N25Q256A), U14
23. Microchip USB3320 USB transceiver PHY , U32
24. Reference clock signal oscillator SiTime SiT8008BI @52.000000 MHz, U33
25. Microchip 24AA025E48 EEPROM for MAC address, U23
    
26. Lattice Semiconductor MachXO2-256HC System Controller CPLD, U2
    

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Table 1: Initial delivery state.

Signals, Interfaces and Pins

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Table 3: SoC's MGT lanes connections to the B2B connectors.

Below are listed MGT banks reference clock sources.

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Table 4: MGT reference clock sources.

JTAG Interface

JTAG interface access is provided through the SoC's PS configuration bank 0 and is available on B2B connector J1.

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Table 5: JTAG interface signals.

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Table 56: System Controller CPLD special purpose I/O pins.

Quad SPI Interface

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

Table 67: MIO-pin assignment of the Quad SPI Flash memory IC.

Gigabit Ethernet Interface

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Table 78: Ethernet PHY interface connections.

USB Interface

USB PHY (U32) is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

Table 89: USB PHY interface connections.

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

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The I²C interface on B2B connector J2 pins 119 (I2C_33_SCL) and 121 (I2C_33_SDA) have has PS_3.3V as reference voltage .The I²C bus works internally on module with reference voltage 1.8V, on the Zynq chip it and is connected to the PS I²C interface via PS MIO bank 500, pins MIO10 and MIO11.Zynq SoC via voltage level translating (3.3V ↔ 1.8V) I²C bus repeater (U17).:

Table 910: MIO-pin Pin assignment of the module's B2B I²C interface
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The on-module Except the RTC (U24), all I²C slave devices are operating with the interface works with reference voltage PS_ 1.8V:

Table 11: MIO-pin assignment of the on-module I²C interface.

Except the on-module RTC (U24), all other on-module I²C slave devices are operating with the reference voltage PS_1.8V. via voltage level translating (3.3V ↔ 1.8V) I²C bus repeater (U17).

I²C addresses for on-board module devices are listed in the table below:

Table 1012:  Module's I²C-interfaces overview.

Boot Process

TE0745 module supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21 (permanent logic high in standard SC-CPLD firmware).

The current boot mode selection will be set by the Zynq's PS MIO pins MIO3...MIO5. The control line 'BOOTMODE' is connected to the 'MIO4' pin, 'BOOTMODE_1' to 'MIO5'.

Following table describes how to set the control lines to configure the desired boot mode:

Table 11: Selectable boot modes.

In delivery state of the SoM the boot mode depends on the configured SC-CPLD firmware. The current mode is set to boot from the QSPI Flash Memory.

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Table 12: Pin description of PLL clock generator Si5338A

Oscillators

The SoC module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

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