Page History

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Lane	Bank	Type	Signal Name	B2B Pin	FPGA Pin
0	112	GTX	MGT_RX0_P MGT_RX0_N MGT_TX0_P MGT_TX0_N	J3-50 J3-52 J3-51 J3-53	MGTHRXP0_112, AB4 MGTHRXN0_112, AB3 MGTHTXP0_112, AA2 MGTHTXN0_112, AA1
1	112	GTX	MGT_RX1_P MGT_RX1_N MGT_TX1_P MGT_TX1_N	J3-56 J3-58 J3-57 J3-59	MGTHRXP1_112, Y4 MGTHRXN1_112, Y3 MGTHTXP1_112, W2 MGTHTXN1_112, W1
2	112	GTX	MGT_RX2_P MGT_RX2_N MGT_TX2_P MGT_TX2_N	J3-62 J3-64 J3-63 J3-65	MGTHRXP2_112, V4 MGTHRXN2_112, V3 MGTHTXP2_112, U2 MGTHTXN2_112, U1
3	112	GTX	MGT_RX3_P MGT_RX3_N MGT_TX3_P MGT_TX3_N	J3-68 J3-70 J3-69 J3-71	MGTHRXP3_112, T4 MGTHRXN3_112, T3 MGTHTXP3_112, R2 MGTHTXN3_112, R1
4	111 ¹⁾	GTX	MGT_RX4_P MGT_RX4_N MGT_TX4_P MGT_TX4_N	J1-23 J1-21 J1-22 J1-20	MGTHRXP0_111, AD8 MGTHRXN0_111, AD7 MGTHTXP0_111, AF8 MGTHTXN0_111, AF7
5	111 ¹⁾	GTX	MGT_RX5_P MGT_RX5_N MGT_TX5_P MGT_TX5_N	J1-17 J1-15 J1-16 J1-14	MGTHRXP1_111, AE6 MGTHRXN1_111, AE5 MGTHTXP1_111, AF4 MGTHTXN1_111, AF3
6	111¹⁾	GTX	MGT_RX6_P MGT_RX6_N MGT_TX6_P MGT_TX6_N	J1-11 J1-9 J1-10 J1-8	MGTHRXP2_111, AC6 MGTHRXN2_111, AC5 MGTHTXP2_111, AE2 MGTHTXN2_111, AE1
7	111¹⁾	GTX	MGT_RX7_P MGT_RX7_N MGT_TX7_P MGT_TX7_N	J1-5 J1-3 J1-4 J1-2	MGTHRXP3_111, AD4 MGTHRXN3_111, AD3 MGTHTXP3_111, AC2 MGTHTXN3_111, AC1

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Clock signal	Bank	Source	FPGA Pin	Notes
MGT_CLK0_P	112	B2B, J3-75	MGTREFCLK0P_112, R6	Supplied by the carrier board.
MGT_CLK0_N	112	B2B, J3-77	MGTREFCLK0N_112, R5	Supplied by the carrier board.
MGT_CLK1_P	112	U16, CLK0A	MGTREFCLK1P_112, U6	On-module Si5338A.
MGT_CLK1_N	112	U16, CLK0B	MGTREFCLK1N_112, U5	On-module Si5338A.
MGT_CLK2_P	111 ¹⁾	B2B, J3-81	MGTREFCLK0P_111, W6	Supplied by the carrier board.
MGT_CLK2_N	111 ¹⁾	B2B, J3-83	MGTREFCLK0N_111, W5	Supplied by the carrier board.
MGT_CLK3_P	111 ¹⁾	U16, CLK3A	MGTREFCLK1P_111, AA6	On-module Si5338A.
MGT_CLK3_N	111 ¹⁾	U16, CLK3B	MGTREFCLK1N_111, AA5	On-module Si5338A.

Table 4: MGT reference clock sources.

¹⁾ Note: MGT bank 111 not available at XC7Z030 Zynq SoC.

JTAG Interface

JTAG interface access is provided through the SoC's PS configuration bank 0 and is available on B2B connector J1.

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Once running, the frequency and other parameters can be changed by programming the device using the I²C-bus connected between the Zynq module (master) and reference clock signal generator (slave).

Si5338A Pin	Signal Name / Description	Connected To	Direction	Note
IN1	CLKIN_P	B2B, J3-76	Input	Reference input clock from base board.
IN2	CLKIN_N	B2B, J3-74	Input	Reference input clock from base board.
IN3	Reference input clock.	Oscillator U21, pin 3	Input	25.000000 MHz oscillator, Si8008BI.
IN4	-	GND	Input	I²C slave device address LSB (0x70 default address).
IN5	-	Not connected.	Input	Not used.
IN6	-	GND	Input	Not used.
CLK0A	MGT_CLK1_P	Zynq Soc U1, pin U6	Output	MGT bank 112 reference clock.
CLK0B	MGT_CLK1_N	Zynq Soc U1, pin U5	Output	MGT bank 112 reference clock.
CLK1A	CLK1_P	B2B, J3-80	Output	Reference clock output to base board.
CLK1B	CLK1_N	B2B, J3-82	Output	Reference clock output to base board.
CLK2A	CLK2_P	B2B, J3-86	Output	Reference clock output to base board.
CLK2B	CLK2_P	B2B, J3-88	Output	Reference clock output to base board.
CLK3A	MGT_CLK3_P	Zynq Soc U1, pin AA6	Output	MGT bank 111 reference clock.
CLK3B	MGT_CLK3_N	Zynq Soc U1, pin AA6	Output	MGT bank 111 reference clock.

Table 14: Programmable quad PLL clock generator inputs and outputs.

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B2B connectors

Include Page

	IN:SS5-ST5 connectors
	IN:SS5-ST5 connectors	5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors	5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors

Variants Currently In Production

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Date

Revision

Contributors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Ali Naseri

TRM revision and update
to new common style

2017-07-19

v.71

Ali Naseri, Jan Kumann

First TRM release.

2017-02-05

v.1

Jan Kumann

Initial document.

Table 24: Document change history.

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Trenz Electronic Documentation

Versions Compared

Old Version 76

New Version 77

Key

JTAG Interface

B2B connectors

Variants Currently In Production