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Storage Device Name

Content

Notes

24AA025E48 EEPROM

User content, not programmed

Valid MAC Address from manufacturer.

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor.

SPI Flash Quad Enable bit

Programmed

-

SPI Flash main array

Demo designNot programmed

-

eFUSE USER

Not programmed

-

eFUSE Security

Not programmed

-
Si5338 OTP NVMDefault settings pre Not programmedOTP not re-programmable after delivery from factory

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TE0745 module supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21 (permanent logic high in standard SC-CPLD firmware).The boot mode selection will be set by the Zynq's PS MIO pins MIO3...MIO5.

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NAND
Boot ModeMIO5 (BOOTMODE_1), SC CPLDMIO4 (BOOTMODE), J2-133MIO3Note

JTAG

000-
NOR001MIO3 pin is shared with QSPI Flash Memory (QSPI-DQ1).

010-
QSPI Flash Memory100standard mode in current configuration.
SD-Card110SD-Card on base board necessary.

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In delivery state of the SoM the boot mode depends on the configured SC-CPLD firmware. The current mode Basically MIO5 is set to boot from the QSPI Flash Memory1 and JTAG is in cascade.

On-board Peripherals

System Controller CPLD

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Bank

Schematic Name

Voltage

Voltage Range

0 (config)VCCIO_0

PL_1.8V, if R67 is equipped
PS_1.8V, if R68 is equipped

-
500 (MIO0)PS_1.8V 1.8V-
501 (MIO1)PS_1.8V1.8V-
502 (DDR3)1.35V1.35V-
12 HRVCCIO_12UserHR: 1.2V to 3.3V
13 HRVCCIO_13UserHR: 1.2V to 3.3V
33 HPVCCIO_33UserHP: 1.2V to 1.8V
34 HPVCCIO_34UserHP: 1.2V to 1.8V
35 HPVCCIO_35UserHP: 1.2V to 1.8V

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 Date

Revision

ContributorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd



Ali Naseri, Jan Kumann, John Hartfiel
  • First TRM release

Table 24: Document change history.

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