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Overview

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Wiki Link: Go to Base Folder of the Module or Carrier, for example : https://wiki.trenz-electronic.de/display/PD/TE0712
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Refer to httpshttp://wiki.trenz-electronic.de/display/PD/<name>org/tem0002-info for the current online version of this manual and other available documentation.

The Trenz Electronic TEM0002-01 SmartBerry with Raspberry Pi form factor, is an industrial-grade module based on Microsemi SmartFusion2 SoC (System on a Chip). The Module has 128MB DDR3 SDRAM, a Gigabit Ethernet PHY, Micro USB,  four PMODs and four Pmods, a GPIO Pin header compatible to the Raspberry Pi pinout and a Micro USB to UART interface. SmartFusion2 combiens combines a 166 MHz Cortex-M3 core with 256 KByte Flash, 80 KByte SRAM  and a 12 kLUT FPGA Core Logiccore logic.

Key Features

• Microsemi SmartFusion2 SoC FPGA (M2S010)
• 128 MByte DDR3 SDRAM
• On board power converters for all needed voltages
• 40 pin header (compatible to Raspberry Pi pinout)
• 4 x 12 pin PMODsPmods
• Gigabit Ethernet PHY with RGMII interface
• JTAG and UART via Micro USB
• 3 pin header for Live Probes
• 2 x User Button
• 2 x status LED

• 1 x  RGB LED

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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Main Components

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Table 1: TEM0002-01 main components.

1. Microsemi SmartFusion2 SoC FPGA, U2
2. USB to
3. Microsemi SmartFusion2 SoC FPGA, U2
4. USB to UART/FIFO (FTDI FT2232H), U3
5. Gigabit ETH connector, J2
6. 4x  2x6 pin PMODPmod, P1, P2, P3, P4
   
7. GPIO pin header compatible to Raspberry Pi, J8
8. Micro USB 2.0, J1
9. EEPROM 4KBIT (M93C66-R), U6
10. 2x User Button, S4, S5
11. RGB LED, D3
12. LED red, D1 and green, D2
13. Live Probe pins, J4
14. Reset jumper, J13
15. JTAG select jumper, J6
16. Board power header, J5
17. 1Gb DDR3/L SDRAM, U5
18. MicroSD memory card connector, J3
19. Gigabit Ethernet PHY, U1

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector JM..

...

MODE Signal State

...

High or open

...

SD Card

...

Low or ground

...

QSPI Interface

The SmartBerry supports configuration of the system via JTAG by the FTDI USB bridge.

Signals, Interfaces and Pins

Table 2: Selecting power-on boot device.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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I/Os

26 I/O signals connected to the SoCs I/O bank and B2B connector: 

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Table x: General overview of PL I/O signals connected to the B2B connectors.

All PS MIO banks are powered by on-module DC-DC power rail. All PL I/O banks have separate VCCO input pins in the B2B connectors, valid VCCO should be supplied from the carrier board.

For detailed information about the pin out, please refer to the Pin-out Tables. 

The configuration of the PS I/Os MIOx, MIOx ... MIOx, ... depend on the carrier board peripherals connected to these pins.

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TO-DO (future):
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MGT Lanes

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MGT lanes should be listed separately, as they are more specific than just general I/Os.  
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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

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• MGT_RX0_P
• MGT_RX0_N
• MGT_TX0_P
• MGT_TX0_N

...

• JM3-8
• JM3-10
• JM3-7
• JM3-9

...

• MGTHRXP0_225, Y2
• MGTHRXN0_225, Y1
• MGTHTXP0_225, AA4
• MGTHTXN0_225, AA3

...

• MGT_RX1_P
• MGT_RX1_N
• MGT_TX1_P
• MGT_TX1_N

...

• JM3-14
• JM3-16
• JM3-13
• JM3-15

...

• MGTHRXP1_225, V2
• MGTHRXN1_225, V1
• MGTHTXP1_225, W4
• MGTHTXN1_225, W3

...

• MGT_RX4_P
• MGT_RX4_N
• MGT_TX4_P
• MGT_TX4_N

...

• JM1-12
• JM1-10
• JM1-6
• JM1-4

...

• MGTHRXP0_224, AH2
• MGTHRXN0_224, AH1
• MGTHTXP0_224, AG4
• MGTHTXN0_224, AG3

...

• MGT_RX5_P
• MGT_RX5_N
• MGT_TX5_P
• MGT_TX5_N

...

• JM1-24
• JM1-22
• JM1-18
• JM1-16

...

• MGTHRXP1_224, AF2
• MGTHRXN1_224, AF1
• MGTHTXP1_224, AF6
• MGTHTXN1_224, AF5

...

provided on the Rasperry Pi compatible header are connected  to banks with 3.3V. Dpending on the configuration of the SoC, also GPIOs of the Microprocessor subsystem can be routet to the SoC Pins.

Table 2: General overview of I/O signals connected to the SoC.

Further I/Os are provided via the Pmod connectors descriebed below.

Pmods

The module provides four 2x6 female Pmod connectors. Two of the headers (P2 and P3) are arranged to use as dual 12 pin Pmod. According to the standard on all four headers Pin 5 and 11 are connected to ground, 6 and 12 to 3.3V.

Table 3: Overview of Pmod signals connected to the SoC.

JTAG Interface

JTAG access to the SoC components is provided through the micro usb connector via the FTDI usb to UART bridge. Depending on the jumper J6 the JTAGSEL signal SW3 switches the JTAG interface to either the FPGA fabric TAP (OPEN, high) or the Cortex-M3 JTAG debug interface (CLOSED, low). JTAG signals are powered by 3.3V.

Table 4: JTAG interface signals.

SD Card Interface

The SD Card interface is connected to bank 2 of the SoC

Table 5: SD Card interface signals and connections.

Ethernet Interface

Table 6: Ethernet PHY signals and connections.

I2C Interface

There are no on-board I²C devices.  For Raspberry Pi compability the device detection I²C bus is routed from the header J8-27/28 to Bank 1 U2-A20/A19 (SDA/SCL). 

Table 7: I²C slave device addresses.

On-board Peripherals

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Components on the Module, like Flash, PLL, PHY...
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DDR Memory

TEM0002 has 1Gb industrial grade DDR3 SDRAM (U5). A 16-bit wide memory bus providing total of 128 MBytes of on-board RAM. Specification is 800 MHz clocking resulting in 1600 Mb/s data rate and timings  of 11-11-11 (CL-T_RCD-T_RP).

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (J2) is provided by  Microsemi VSC8531 chip (U1). The Ethernet PHY RGMII interface is connected to bank 6 of the Microsemi SOC. I/O voltage is fixed at 1.5V. The reference clock input of the PHY is supplied from an external 25.000000 MHz oscillator (U11).

Oscillators

The module has following reference clock signals provided by on-board oscillators:

Table 8: Reference clock signals.

¹In REV02, Y1 will be replaced by a 12 MHz crystal.

On-board LEDs

Table 9: On-board LEDs.

On-board Buttons

Table 10: On-board Buttons.

Power and Power-On Sequence

There is no specific power on Sequence. Just supply with 5V via the micro USB J1 or the J5 PWR_IN with current rating sufficient for your Design.

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Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Table 11: Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

Power Distribution Dependencies

Power Rails

Table 12: Module power rails.

Bank Voltages

Table 13:  I/O bank voltages.

Variants Currently In Production

Table 14

Table x: MGT lanes.

Below are listed MGT banks reference clock sources.

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Table x: MGT reference clock sources.

JTAG Interface

JTAG access to the ... is provided through B2B connector .... 

...

JTAG Signal

...

B2B Connector Pin

...

Table 5: JTAG interface signals.

System Controller CPLD I/O Pins

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

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Table x: System Controller CPLD I/O pins.

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For the detailed function of the pins and signals, the internal signal assignment and implemented logic, look to the Wiki reference page SC CPLD of this module or into the bitstream file of the SC CPLD.
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Quad SPI Interface

Following line is just an example, change it to your needs.

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

Note that table column says "Signal Name", it should match the name used on the schematic.

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Table x: Quad SPI interface signals and connections.

SD Card Interface

Describe SD Card interface  shortly here if the module has one...

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Table x: SD Card interface signals and connections.

Ethernet Interface

On board Gigabit Ethernet PHY is provided with ...

Ethernet PHY connection

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Table x: ...

USB Interface

USB PHY is provided with ...

...

Table x: ...

The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

On-board I²C devices are connected to MIO.. and MIO.. which are configured as I²C... by default. I²C addresses for on-board devices are listed in the table below:

...

Table x: I²C slave device addresses.

On-board Peripherals

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System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

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DDR Memory

By default TE0xxx module has ... DDRx SDRAM chips arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

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25.000 MHz

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Table : Reference clock signals.

On-board LEDs

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U2-H5 Bank 7, U2-F6 Bank 7, U2-H6 Bank 7

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Table : On-board LEDs.

Power and Power-On Sequence

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If power sequencing and distribution is not so much, you can join both sub sections together
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Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

...

Table : Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The on-board voltages of the TE07xx SoC module will be powered-up in order of a determined sequence after the external voltages '...', '...' and '...' are available. All those power-rails can be powered up, with 3.3V power sources, also shared. <-- What?

Power Distribution Dependencies

Regulator dependencies and max. current.

Put power distribution diagram here...

Figure : Module power distribution diagram.

See Xilinx data sheet ... for additional information. User should also check related base board documentation when intending base board design for TE07xx module.

Power-On Sequence

The TE07xx SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Put power-on diagram here...

Figure : Module power-on diagram.

Voltage Monitor Circuit

If the module has one, describe it here...

Power Rails

NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.

...

Power Rail Name

...

B2B JM1 Pins

...

B2B JM2 Pins

...

Direction

...

VBAT_IN

...

Table : Module power rails.

Different modules (not just 4 x 5 cm ones) have different type of connectors with different specifications. Following note is for Samtec Razor Beam™ LSHM connectors only, but we should consider adding such note into included file in Board to Board Connectors section instead of here.

Bank Voltages

...

Bank

...

Voltage

...

Voltage Range

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Table : Module PL I/O bank voltages.

Board to Board Connectors

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Variants Currently In Production

NB! Note that here we look at the module as a whole, so you just can't rely only on junction temperature or max voltage of particular SoC or FPGA chip on the module. See examples in the table below.

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Operating Temperature

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Table : Module variants.

Technical Specifications

Absolute Maximum Ratings

Table 15: Module absolute maximum ratings.

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¹Boundary determined by the specification of the buttons, all other components have at least a range of -40°C to  85°C.

Recommended Operating Conditions

Table 16Table : Module recommended operating conditions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Extended grade: 0°C to +85°C.

...

¹Upper bound is determined by the buttons, all other components have at least a upper bound of 85 °C.

Operating Temperature Ranges

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 85 mm × 56 mm.  Please download the assembly diagram for exact numbers.

• PCB thickness: 1.55 mm.

• Highest part on PCB: top approx. 13.3 mm (Ethernet), bottom 1.57mm (SD-Card)Please download the step model for exact numbers.

All dimensions are given in millimeters.Image RemovedImage Removed

Scroll Title
anchor TD_TEM0002 title Figure 4: Module physical dimensions drawing.
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Revision History

Hardware Revision History

Table 17: Module hardware revision history.

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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Put picture of actual PCB showing model and hardware revision number here...

with the module model number separated by the dash.

Figure 5Figure : Module hardware revision number.

Document Change History

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Table 18: Document change history.

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