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Excerpt
  • PetaLinux
  • SD
  • ETH
  • USB
  • I2C
  • RTC
  • FMeterSI5338
  • Modified FSBL for SI5338 programming
  • Special FSBL for QSPI programming Initialisation with FSBL

Revision History

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DateVivadoProject BuiltAuthorsDescription
2018-01-242017.4TE0820-test_board-vivado_2017.4-build_05_20180124085247.zip
TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180124085303.zip
John AHrtfiel
  • rework board part files
  • solved  USB, QSPI and PHy issue
2017-11-212017.2TE0820-test_board-vivado_2017.2-build_05_20171121160552.zip
TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171121160606.zip
John Hartfiel
  • solved SD SDX Cards Problem
  • Separate csv name for all assembly variants
2017-11-202017.2TE0820-test_board-vivado_2017.2-build_05_20171120162931.zip
TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171120162851.zip
John Hartfiel
  • solved SD WP Problem
2017-10-192017.2TE0820-test_board-vivado_2017.2-build_05_20171019104824.zip
TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171019104837.zip
John Hartfiel
  • initial release

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2017.4
IssuesDescriptionWorkaroundTo be fixed version
USB2.0works only with USB3.0 enabled in Vivado Designenable USB3.0---
Boot Modefor 4x5 carrier compatibility, currently 2 different CPLD Firmware files are available. Reprogram CPLD (TE0820 CPLD Firmware)2017.4 with special FSBL
------------PHY LEDPHY LED is on X1 instead X0 as described--

Requirements

Software

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SoftwareVersionNote
Vivado2017.24needed
SDK2017.24needed
PetaLinux2017.24needed
SI5338 Clock Builder---optional

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Reference Design is available on:

Design Flow

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  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image RemovedImage Added
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (bl31.elf, uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
        Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
  7. Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

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Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.

QSPI

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Optional for Boot.bin on QSPI Flash and image.ub on SD.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd"

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  1. or if not created, create with "vivado_

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  1. create_project_guimode.cmd"

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  1. Type on Vivado TCL Console:

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  1. TE::pr_program_flash_

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  1. binfile -swapp

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  1. u-boot

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  1. Note:

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  1. To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
  2. Copy image.ub on SD-Card
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  3. Insert SD-Card


SD

Use Use this description for CPLD Firmware with QSPI SD Boot selectable.

  1. Set Boot Mode to JTAG (See Carrier and TE0820 CPLD description)
  2. Connect JTAG
  3. Power ON PCB
  4. Program Flash
    1. Open Vivadi HW-Manager (use Auto Connect)
    2. Right Click on FPGA Device (xczu...) and "Add Configuration Memory Device"
    3. Select "mt25qu256-qspi-x8-dual_parallel"
    4. On "Program Configuration Memory Device":
      1. Set Configuration file: "prebuilt\boot_images\<short name>\u-boot\BOOT.bin"
      2. Set Zynq FSBL: "prebuilt\software\<short name>\zynqmp_fsbl.elf"
      3. Press OK
    5. Note: Other possible ways, see Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
               Do not use Trenz Script for Programming at the moment. Dual Parallel Flash Scripts support is not implemented.
  5. Copy image.ub on SD-Card.
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  6. Power OFF PCB
  7. Set Boot Mode to QSPI
    • Depends on Carrier, see carrier TRM.

SD

Use this description for CPLD Firmware with SD Boot selectable.

  1. Copy image.ub and Boot.bin on SD-Card.
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card or QSPI as Boot Mode (Depends on used programming variant)
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. ZynqMP Boot ROM loadsPMU Firmware and  FSBL from SD into OCM, 2. FSBL loads ATF(bl31.elf)and U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 0 Bus type: i2cdetect -y -r 0
    2. RTC check: dmesg | grep rtc
    3. ETH0 works with udhcpc
    4. USB type  "lsusb" or connect USB2.0 device

Vivado HW Manager

SI5338_CLK0 Counter: 

  1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
    1. Set radix from VIO signals to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz

SI5338 CLK is configured to  200MHz by default.

PHY LEDS

CPLD Firmware:

 Image Removed

System Design - Vivado

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PS Interfaces

Activated interfaces:

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  1. Copy image.ub and Boot.bin on SD-Card.
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card or QSPI as Boot Mode (Depends on used programming variant)
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. ZynqMP Boot ROM loadsPMU Firmware and  FSBL from SD/QSPI Flash into OCM, 2. FSBL loads ATF(bl31.elf)and U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 0 Bus type: i2cdetect -y -r 0
    2. RTC check: dmesg | grep rtc
    3. ETH0 works with udhcpc
    4. USB type  "lsusb" or connect USB2.0 device

Vivado HW Manager

SI5338_CLK0 Counter: 

  1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
    1. Set radix from VIO signals to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz

SI5338 CLK is configured to  200MHz by default.

PHY LEDS

CPLD Firmware:

 Image Added

System Design - Vivado

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PS Interfaces

Activated interfaces:

TypeNote
DDR
QSPIMIO
SD0MIO
SD1MIO
I2C0MIO
UART0MIO
GPIO0MIO
SWDT0..1
TTC0..3
GEM3MIO
USB0MIO


Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design

Design specific constrain

Code Block
languageruby
title_i_io.xdc
set_property PACKAGE_PIN K9 [get_ports {SI5338_

Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design

Design specific constrain

Code Block
languageruby
title_i_io.xdc
set_property PACKAGE_PIN K9 [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property DIFF_TERM TRUE [get_ports {SI5338_CLK0_D_clk_p[0]}]

set_property PACKAGE_PIN H1 [get_ports {x0_phy_ledfirmware[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x0_phy_ledfirmware[0]}]
set_property PACKAGE_PIN J1 [get_ports {x1_phy_firmwareled[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x1_phy_firmwareled[0]}]

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

SDK Projects

Application

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zynqmp_fsbl

TE modified 2017.2 4 FSBL

Changes:

  • Si5338 Configuration, ETH+OTG Reset over GPIO see xfsbl_board.c and , xfsbl_board.h
  • Add register_map.h, si5338.c, si5338.h

PMU

zynqmp_fsbl_flash

TE modified 2017.4 FSBL

Changes:

  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

zynqmp_pmufw

Xilinx default Xilinx default PMU firmware.

Hello

...

TE0820

Hello TE0820 is a Xilinx default Hello world example. Note: Hello World output appears only on time on power up. World example as endless loop instead of one console output.

U-Boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

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For PetaLinux installation and  project creation, follow instructions from:

Config

No changes.

U-Boot

  • Change platform-top.h
Code Block
languagejs
#include <configs/platform-auto.h>

/* Bugfix to select SD1 instead of eMMC(SD0) */
#define CONFIG_EXTRA_ENV_SETTINGS \
    SERIAL_MULTI \ 
    CONSOLE_ARG \ 
    PSSERIAL0 \ 
    "nc=setenv stdout nc;setenv stdin nc;\0" \ 
    "ethaddr=00:0a:35:00:22:01\0" \
    "importbootenv=echo \"Importing environment from SD ...\"; " \ 
        "env import -t ${loadbootenv_addr} $filesize\0" \ 
    "loadbootenv=load mmc $sdbootdev:$partid ${loadbootenv_addr} ${bootenv}\0" \ 
    "sd_uEnvtxt_existence_test=test -e mmc $sdbootdev:$partid /uEnv.txt\0" \ 
    "uenvboot=" \ 
    "if run sd_uEnvtxt_existence_test; then" \ 
        "run loadbootenv" \ 
        "echo Loaded environment from ${bootenv};" \ 
        "run importbootenv; \0" \ 
    "sdboot=echo boot Petalinux; run uenvboot ; mmcinfo && fatload mmc 1 ${netstart} ${kernel_img} && bootm \0" \ 
    "autoload=no\0" \ 
    "clobstart=0x10000000\0" \ 
    "netstart=0x10000000\0" \ 
    "dtbnetstart=0x11800000\0" \ 
    "loadaddr=0x10000000\0" \ 
    "boot_img=BOOT.BIN\0" \ 
    "load_boot=tftpboot ${clobstart} ${boot_img}\0" \ 
    "update_boot=setenv img boot; setenv psize ${bootsize}; setenv installcmd \"install_boot\"; run load_boot ${installcmd}; setenv img; setenv psize; setenv installcmd\0" \ 
    "install_boot=mmcinfo && fatwrite mmc 1 ${clobstart} ${boot_img} ${filesize}\0" \ 
    "bootenvsize=0x40000\0" \ 
    "bootenvstart=0x100000\0" \ 
    "eraseenv=sf probe 0 && sf erase ${bootenvstart} ${bootenvsize}\0" \ 
    "jffs2_img=rootfs.jffs2\0" \ 
    "load_jffs2=tftpboot ${clobstart} ${jffs2_img}\0" \ 
    "update_jffs2=setenv img jffs2; setenv psize ${jffs2size}; setenv installcmd \"install_jffs2\"; run load_jffs2 test_img; setenv img; setenv psize; setenv installcmd\0" \ 
    "sd_update_jffs2=echo Updating jffs2 from SD; mmcinfo && fatload mmc 1:1 ${clobstart} ${jffs2_img} && run install_jffs2\0" \ 
    "install_jffs2=sf probe 0 && sf erase ${jffs2start} ${jffs2size} && " \ 
        "sf write ${clobstart} ${jffs2start} ${filesize}\0" \ 
    "kernel_img=image.ub\0" \ 
    "load_kernel=tftpboot ${clobstart} ${kernel_img}\0" \ 
    "update_kernel=setenv img kernel; setenv psize ${kernelsize}; setenv installcmd \"install_kernel\"; run load_kernel ${installcmd}; setenv img; setenv psize; setenv installcmd\0" \ 
    "install_kernel=mmcinfo && fatwrite mmc 1 ${clobstart} ${kernel_img} ${filesize}\0" \ 
    "cp_kernel2ram=mmcinfo && fatload mmc 1 ${netstart} ${kernel_img}\0" \ 
    "dtb_img=system.dtb\0" \ 
    "load_dtb=tftpboot ${clobstart} ${dtb_img}\0" \ 
    "update_dtb=setenv img dtb; setenv psize ${dtbsize}; setenv installcmd \"install_dtb\"; run load_dtb test_img; setenv img; setenv psize; setenv installcmd\0" \ 
    "sd_update_dtb=echo Updating dtb from SD; mmcinfo && fatload mmc 1:1 ${clobstart} ${dtb_img} && run install_dtb\0" \ 
    "fault=echo ${img} image size is greater than allocated place - partition ${img} is NOT UPDATED\0" \ 
    "test_crc=if imi ${clobstart}; then run test_img; else echo ${img} Bad CRC - ${img} is NOT UPDATED; fi\0" \ 
    "test_img=setenv var \"if test ${filesize} -gt ${psize}\\; then run fault\\; else run ${installcmd}\\; fi\"; run var; setenv var\0" \ 
    "netboot=tftpboot ${netstart} ${kernel_img} && bootm\0" \ 
    "default_bootcmd=run cp_kernel2ram && bootm ${netstart}\0" \ 
""

Device Tree

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For PetaLinux installation and  project creation, follow instructions from:

Config

No changes.

U-Boot

  • Change platform-top.h
Code Block
languagejs
#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000

#define DFU_ALT_INFO_RAM \
                "dfu_ram_info=" \
        "setenv dfu_alt_info " \
        "image.ub ram $netstart 0x1e00000\0" \
        "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
        "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"

#define DFU_ALT_INFO  \
                DFU_ALT_INFO_RAM

/*Required for uartless designs */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
#ifdef CONFIG_DEBUG_UART
#undef CONFIG_DEBUG_UART
#endif
#endif

/*select sd instead of mmc for autoboot */


#define CONFIG_BOOTCOMMAND    "run uenvboot;  mmcinfo && fatload mmc 1 ${netstart} ${kernel_img};bootm ${netstart}"



Device Tree

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
};


/* SDIO */

&sdhci1 {
   disable-wp;
   no-1-8-v;
};

/* ETH PHY */
&gem3 {

    status = "okay";
  ethernet_phy0: ethernet-phy@0 {
        compatible = "marvell,88e1510";
        device_type = "ethernet-phy";
            reg = <1>;
    };
};
/* USB 2.0 */

&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    maximum-speed = "high-speed";
    /delete-property/phy-names;
    /delete-property/phys;
    /delete-property/snps,usb3_lpm_capable;
};
Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
};


/* SDIO */

&sdhci1 {
   disable-wp;
   no-1-8-v;
};

/* ETH PHY */
&gem3 {

    status = "okay";
  ethernet_phy0: ethernet-phy@0 {
        compatible = "marvell,88e1510";
        device_type = "ethernet-phy";
            reg = <1>;
    };
};


/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "n25q256a";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};

/* DMA not used: Reduce error messages on linux.*/

&lpd_dma_chan1 {
    status = "disabled";
};
&lpd_dma_chan2 {
    status = "disabled";
};
&lpd_dma_chan3 {
    status = "disabled";
};
&lpd_dma_chan4 {
    status = "disabled";
};
&lpd_dma_chan5 {
    status = "disabled";
};
&lpd_dma_chan6 {
    status = "disabled";
};
&lpd_dma_chan7 {
    status = "disabled";
};
&lpd_dma_chan8 {
    status = "disabled";
};

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DateDocument RevisionAuthorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
current-version
current-version
prefixv.


 

Page info
modified-user
modified-user

  • Release 2017.4
2018-01-10v.24John Hartfiel
  • Update Known Issues
2017-12-20v.23John Hartfiel
  • Typo correction
  • Update HW Module Table Description
2017-11-21

v.19

John Hartfiel
  • Design Update
2017-11-20v.18John Hartfiel
  • Design Update
  • Add Variants with 128MB Flash
2017-11-13v.16John Hartfiel
  • Update Carrier sections
2017-11-06v.15John Hartfiel
  • Typo corrected
2017-10-23v.13John Hartfiel
  • Update Key Features section
  • Style Update Additional Software section
2017-10-19
v.9
John Hartfiel
  • Release 2017.2
2017-09-11v.1

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created-user
created-user

Initial release
 All

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modified-users

 

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