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Overview

Refer to https://wiki.trenz-electronic.de/display/DRAFT/TE0723+TRM for downloadable version of this manual and additional technical documentation of the product.
 

The Trenz Electronic TE0723 is a Arduino compatible FPGA module based on the Xilinx Zynq XC7Z010 SoC.

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Figure 1: TE0723 block diagram.

Main Components

Figure 2: Main components of the TE0723 module.

1. Xilinx Zynq XC7Z010 SoC, U1
2. 4 Gbit DDR3L 256M x 16 SDRAM, U2
3. 16 MByte quad SPI Flash memory, U5

4. High-speed CMOS logic analog multiplexer/demultiplexer, U10

5. 1 MHz low-power operational amplifier, U11
6. Dual high-speed USB to multipurpose UART/FIFO, U3
7. 0.5A dual-channel current-limited power switch, U21
8. Low-power programmable oscillator @ 12.000000 MHz, U7
9. 2-Kbit Microwire compatible serial EEPROM, U6
10. 10-pin header, J1
11. 8-pin header, J2
12. 10-pin header, J3
13. Analog input header, J4
14. 2 x 4-pin header, J5
15. PMod 2x6 interface header, J6
16. USB host mode jumper, J7
17. Micro USB 2.0 Type-B receptacle, J8
18. Micro USB 2.0 Type-B receptacle, J9
19. Micro SD card connector with detect signal, J10
20. Analog input select jumper, J11
21. 5V supply power input, J12
22. Reset switch, S1
23. Red LED, D2
24. Green LED, D6
25. Green LED, D7
26. Ultra-low supply-current voltage monitor, U23

27. 1A PowerSoC DC-DC converter (3.3 V), U20

28. 1A PowerSoC DC-DC converter (1.8 V, U19
29. 1A PowerSoC DC-DC converter (1.35 V), U16
30. Hi-speed USB 2.0 ULPI transceiver, U18
31. Low-power programmable oscillator @ 52.000000 MHz, U14
32. 1A PowerSoC DC-DC converter (1.0 V), U17
33. JTAG interface testpoints, TP1-TP4

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

The 7 boot mode strapping pins on the TE0723 module are set to boot the system from quad SPI Flash only. For additional information refer to the TE0723 schematic and Xilinx UG585 Zynq-7000 All Programmable SoC Technical Reference Manual (MIO2 ... MIO8) of the Xiliny Zynq Z-7010 device are hardware programmed on the board. They are evaluated by the Zynq device soon after the 'POR_B'.signal is deasserted to begin the boot process (see section "Boot Mode Pin Settings" .You may also refer to this TE0723 reference design for some Boot Process tipsof Xilinx manual UG585).

The TE0723 Zynq board is hardware programmed to boot initially from the on-board QSPI Flash memory U5. The JTAG interface of the module is provided for storing the data to the QSPI Flash memory through the Zynq device.

Signals, Interfaces and Pins

I/O Signals

Overview of the Zynq SoC 's PS/PL banks I/O signals connected to the external connectors:

Table 2: Overview of the Zynq SoC's PS/PL banks I/O signals

Zynq SoC I/O Banks

Table 3: General overview of Zynq SoC PL/PS I/O banks

JTAG Interface

JTAG access to the Xilinx Zynq XC7Z010 SoC is provided through FTDI USB/UART FIFO bridge connected to the J9 Micro USB USB2 connector J9.

Quad SPI Interface

Quad SPI Flash (U5) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

Table 34: Quad SPI interface signals and connections.

SD Card Interface

TE0723 module has on-board 3.3V SD Card socket (J10) with card detect switch wired to the SoC PS MIO bank 500.

Table 4: SD card socket signals.

USB Interface

Table 5: USB interface.

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Table 6: ESP8266 Wi-Fi module interface.

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