Page History
...
HTML |
---|
<!-- Template Revision 1.66 (HTML comments will be not displayed in the document, no need to remove them. For Template/Skeleton changes, increase Template Revision number. So we can check faster, if the TRM style is up to date). --> |
Scroll Ignore |
---|
Download PDF version of this document. |
HTML |
---|
<!-- General Notes: If some section is CPLD firmware dependent, make a note and if available link to the CPLD firmware description. It's in the TE shop download area in the corresponding module -> revision -> firmware folder. --> |
...
Scroll pdf ignore | |
---|---|
Table of Contents
|
Overview
HTML |
---|
<!--
Wiki Link: Go to Base Folder of the Module or Carrier, for example : https://wiki.trenz-electronic.de/display/PD/TE0712
--> |
Scroll Only (inline) |
---|
Refer to https://wiki.trenz-electronic.de/display/PD/TEB0911+TRM for the current online version of this manual and other available documentation. |
The Trenz Electronic TEB0911 UltraRack+ board is an industrial-grade motherboard integrating a Xilinx Zynq UltrascaleUltraScale+ MPSoC with 4 GByte Flash memory for configuration and operation, DDR4-SDRAM SODIMM SO-DIMM socket with 64-bit wide data bus, 24 22 MGT Lanes lanes and powerful switch-mode power supplies for all on-board voltages. . The motherboard TEB0911 board exposes the pins of the Zynq MPSoC 's pins to to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq UltrascaleUltraScale+ MPSoC and for developing purposes. The motherboard board is capable to be fitted to a dedicated enclosure. On , whereby on the enclosure's rear and front panel, I/O's, LVDS-pairs and MGT interfaces lanes are accessible through 6 on-board FMC connectors and other standard high-speed interfaces for , namely USB3.0, SFP+, SSD, GbE, etc.
Key Features
- Single 24V main power supply
- 2x USB3 A Connector (Superspeed Host Port (Highspeed in USB2 mode))
- Gigabit Ethernet RGMII PHY with RJ45 MegJack
- Dual SFP+ Connector (2x1 Cage)
- DDR4-SDRAM SODIMM socket (64bit bus width)
- SSD (Solid State Disk) Connector
- CAN FD Transceiver (10 Pin IDC connector and 6-pin header)
- 1x DisplayPort
- 4x On-board configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT)
- All carrier board peripherals' I²C interfaces muxed to MPSoC's I²C interface
- 6x FMC HPC Connectors
- 6x FMC Fans
- 3x Optional 4-wire PWM fan connectors
- 10 output programmable PLL clock generator Si5345A
- Quad programmable PLL clock generator SI5338A
- 1x SMA coaxial connectors for reference clock signal input
- MicroSD-Socket (bootable)
- 32 Gbit (4 GByte) on-board eMMC flash (8 banks a 4 Gbit)
- System Controller CPLD Lattice MachXO2 7000 HC
- 2x JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for programming MPSoC and SC CPLD
- On-board DC-DC PowerSoCs and LDOs
Additional assembly options are available for cost or performance optimization upon request.
Block Diagram
Put your block diagram here...
...
anchor | Figure_1 |
---|---|
title | Figure 1: TEB0911-03 block diagram |
Main Components
...
HTML |
---|
<!--
Use short link the Wiki Ressource page: for example:
http://trenz.org/te0720-info
List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects
--> |
Scroll Only (inline) |
---|
Refer to http://trenz.org/teb0911-info for the current online version of this manual and other available documentation.
|
Key Features
- Zynq UltraScale+ MPSoC
- ZU6,ZU9 or ZU15 on 1156 Pin Package
- 64bit DDR4 SODIMM (PS connected)
- M2 PCIe SSD (1-Lane)
- eMMC (bootable)
- Dual QSPI Flash (bootable)
- System Controller(LCMXO2-7000HC)
- Power Sequencing
- IO Expander
- Configurable PLLs
- GTH/GTP Reference CLKs
Front Panel
- 4 x FMC
- 4 GTH per FMC
- 68 ZynqMP PL IO per FMC
- DisplayPort (2-Lanes)
- RJ34 ETH + Dual USB3 Combo
- Dual Stack SFP+
- SD (bootable)
- Status LEDs
Back Panel
- 2 x FMC
- 4/2 GTH
- 12 ZynqMP PL IO per FMC
- 56 SC IO per FMC
- USB JTAG/UART ZynqMP
- USB JTAG/GPIO FMC
- CAN FD (DB9 Connector)
- SMA (external CLK)
- 5polig 24V power connector
Additional assembly options are available for cost or performance optimization upon request.
Block Diagram
Scroll Title | ||||
---|---|---|---|---|
|
Add description list of PCB labels here...
Initial Delivery State
...
Storage device name
...
Content
...
Notes
...
Table 1: Initial delivery state of programmable devices on the module.
Boot Process
For the boot process prior to powering up the board settings must be done via DIP-Switch S3-3 and S3-4. Four boot modes can be selected:
...
32-bit addressing, configured with dual on-board QSPI Flash Memory.
...
Table 2: Available boot modes of the on-board Zynq MPSoC
Refer also to the documentation of the SC CPLD firmware of the TEB0911 board, section boot mode.
Signals, Interfaces and Pins
HTML |
---|
<!--
Connections and Interfaces or B2B Pin's which are accessible by User
--> |
FMC Connectors
The TEB0911 Ultrarack+ offers 6 FMC (FPGA Mezzanine Card) connectors which provides as an ANSI/VITA 57.1 standard a modular interface to the MPSoCs FPGA and exposes numerous of its I/O pins and MGT Lanes for use by other mezzanine modules and expansion cards.
The connector supports single ended and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.
Following diagram gives an overview of the FMC connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller CPLD U27:
...
anchor | Figure_3 |
---|---|
title | Figure 3: General overview of the FMC connectors |
...
HTML |
---|
<!--
MGT lanes should be listed separately, as they are more specific than just general I/Os.
--> |
Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the FMC connectors A - F:
...
FMC A
FMC A Interfaces:
...
J10
...
'FMCA_PG_C2M', 'FMCA_PG_M2C', 'FMCA_PRSNT'
...
FMC A MGT Lanes:
...
J10
(FMC A)
...
- B128_RX0_P
- B128_RX0_N
- B128_TX0_P
- B128_TX0_N
...
J10-C6
J10-C7
J10-C2
J10-C3
...
MGTHRXP0_128, T33
MGTHRXN0_128, T34
MGTHTXP0_128, T29
MGTHTXN0_128, T30
...
- B128_RX1_P
- B128_RX1_N
- B128_TX1_P
- B128_TX1_N
...
J10-A2
J10-A3
J10-A22
J10-A23
...
MGTHRXP1_128, P33
MGTHRXN1_128, P34
MGTHTXP1_128, R31
MGTHTXN1_128, R32
...
- B128_RX2_P
- B128_RX2_N
- B128_TX2_P
- B128_TX2_N
...
J10-A6
J10-A7
J10-A26
J10-A27
...
MGTHRXP2_128, N31
MGTHRXN2_128, N32
MGTHTXP2_128, P29
MGTHTXN2_128, P30
...
- B128_RX3_P
- B128_RX3_N
- B128_TX3_P
- B128_TX3_N
...
J10-A10
J10-A11
J10-A30
J10-A31
...
MGTHRXP3_128, M33
MGTHRXN3_128, M34
MGTHTXP3_128, M29
MGTHTXN3_128, M30
| ||||||||||||||||||||||||||||||
|
Main Components
Scroll Title | ||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||
|
- SFP+ 2x1 cage with integrated LED light pipes, J9
- DisplayPort connector, J12
- USB3 A 2x , RJ45 1x (stacked), J13
- FMC connector (FMC B), J4
- FMC B cooling fan, M2
- FMC connector (FMC C), J8
- FMC C cooling fan, M3
- FMC connector (FMC D), J7
- FMC D cooling fan, M4
- FMC connector (FMC E), J6
- FMC E cooling fan, M5
- I²C programming header of on-board PLL clock generator U17, J22
- 4-Wire PWM fan connector, J23
- Main Power Jack 24V, J1
- CAN bus D-SUB 9-pin male connector, J3
- CAN bus 6-pin header male, J15
- XMOD JTAG header for access to System Controller CPLD, J35
- XMOD JTAG header for access to Zynq MPSoC, J24
- 4-Wire PWM fan connector, J33
- Battery Holder CR1220, B1
- SMA coaxial connector (PLL Si5345A U17 clock input), J25
- Push Button, S1
- Push Button, S2
- DDR4 SO-DIMM socket, U3
- 4-bit DIP-switch, S4
- 4-bit DIP-switch, S3
- FMC connector (FMC A), J10
- FMC A cooling fan, M1
- FMC connector (FMC F), J21
- FMC F cooling fan, M6
- NGFF M.2 PCIe socket (Key M), U2
- SD Card socket, J11
- User LEDs (3x green, 1x red) with LED light pipe, D13 ... D16
- Green LEDs dedicated to USB3 hub U4, D17 ... D19
- Red LED indicating FPGAs 'DONE' signal, D6
- 4-Wire PWM fan connector, J2
- Xilinx Zynq Ultrascale+ MPSoC, U1
Initial Delivery State
Storage device name | Content | Notes |
---|---|---|
User configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT) | Empty | Not programmed |
USB3 HUB Configuration EEPROM (Microchip 24LC128-I/ST) | Empty | Not programmed |
Si5338A programmable PLL NVM OTP | Empty | Not programmed |
Si5345A programmable PLL NVM OTP | Empty | Not programmed |
eMMC Flash memory | Empty | Not programmed |
2x QSPI Flash memory | Empty | Not programmed |
Table 1: Initial delivery state of programmable devices on the module
Boot Process
For the boot process prior to powering up the board settings must be done via DIP-Switch S3-3 and S3-4. Four boot modes can be selected:
S3-3 (SC_SW1) | S3-4 (SC_SW2) | MIO Location | Description | Notes |
---|---|---|---|---|
OFF | OFF | MIO[43:38] | SD1 Boot Mode (SD-Card on J11) | Supports SD 2.0 |
OFF | ON | MIO[29:26] | PJTAG0 | PS JTAG connection 0 option |
ON | OFF | MIO[12:0] | QSPI32 | 32-bit addressing, configured with dual on-board QSPI Flash Memory |
ON | ON | - | JTAG | Dedicated PS interface |
Table 2: Available boot modes of the on-board Zynq MPSoC
Refer also to the documentation of the SC CPLD firmware of the TEB0911 board, section 'boot mode'.
Signals, Interfaces and Pins
HTML |
---|
<!--
Connections and Interfaces or B2B Pin's which are accessible by User
--> |
FMC Connectors
The TEB0911 Ultrarack+ offers 6 FMC (FPGA Mezzanine Card) connectors which provides as an ANSI/VITA 57.1 standard a modular interface to the MPSoCs FPGA and exposes numerous of its I/O pins and MGT lanes for use by other mezzanine modules and expansion cards.
The connector supports single ended and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.
Following diagram gives an overview of the FMC connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller CPLD U27:
Scroll Title | ||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||
|
HTML |
---|
<!--
MGT lanes should be listed separately, as they are more specific than just general I/Os.
--> |
Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the FMC connectors A - F:
Anchor FMC A FMC A
FMC A
FMC A Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage |
---|
...
FMC A Clock Signals:
...
J10
(FMC A)
...
- B128_CLK0_P
- B128_CLK0_N
...
J10-D4
J10-D5
...
MGTREFCLK0P_128, R27
MGTREFCLK0N_128, R28
...
FMC A VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J10 (FMC A) | FMCA_3V3 | J10-D36 | DCDC U32, | Enable by SC CPLD U27, bank 2, pin Y18 |
3V3SB | J10-D32 | DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V_FMC_AF | J10-C35 | DCDC U51, | - | |
FMCAF_1V8 | J10-H40 | DCDC U39, | Enable by SC CPLD U27, bank 2, pin W19 |
...
I/O | 12 | 6 | Bank 44 HD | FMCAF_1V8 | - | |
56 | 28 | SC CPLD U27 Bank 1 | FMCAF_1V8 | - | ||
I²C | 2 | - | I²C-Switch U37 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 128 GTH | - | 4x MGT lanes | |
Clock Input | - | 1 | Bank 128 GTH | - | 1x Reference clock input to MGT bank | |
Control Signals | 3 | - | SC CPLD U27 Bank 0 | 3.3VSB | 'FMCA_PG_C2M', 'FMCA_PG_M2C', 'FMCA_PRSNT' |
Table 3: FMC A connector interfaces
FMC A MGT Lanes:
FMC | MGT Lane | Bank | Type | Signal Schematic Name | FMC Connector Pin | FPGA Pin |
---|
FMC A Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J10 (FMC A) | M1 | Enable by SC CPLD U27, bank 2, pin Y19 | - |
Table 7: FMC A connector cooling fan
...
FMC F
FMC F Interfaces:
...
J21
...
'FMCF_PG_C2M', 'FMCF_PG_M2C', 'FMCF_PRSNT'
...
FMC F MGT Lanes:
...
J21
(FMC F)
...
- B129_RX0_P
- B129_RX0_N
- B129_TX0_P
- B129_TX0_N
...
J21-C6
J21-C7
J21-C2
J21-C3
...
MGTHRXP0_129, L31
MGTHRXN0_129, L32
MGTHTXP0_129, K29
MGTHTXN0_129, K30
0 | 128 | GTH |
| J10-C6 | MGTHRXP0_128, T33 | |
1 | 128 | GTH |
| J10-A2 | MGTHRXP1_128, P33 | |
2 | 128 | GTH |
| J10-A6 | MGTHRXP2_128, N31 | |
3 | 128 | GTH |
| J10-A10 | MGTHRXP3_128, M33 |
Table 4: FMC A connector MGT lanes
FMC A Clock Signals:
FMC | Signal Schematic Name | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J10 (FMC A) |
| 128 | J10-D4 | MGTREFCLK0P_128, R27 | Supplied by attached module |
Table 5: FMC A connector clock signal input
FMC A VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J10 (FMC A) | FMCA_3V3 | J10-D36 | DCDC U32, | Enable by SC CPLD U27, bank 2, pin Y18 |
3V3SB | J10-D32 | DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V_FMC_AF | J10-C35 | DCDC U51, | - | |
FMCAF_1V8 | J10-H40 | DCDC U39 |
...
- B129_RX1_P
- B129_RX1_N
- B129_TX1_P
- B129_TX1_N
...
J21-A2
J21-A3
J21-A22
J21-A23
...
MGTHRXP1_129, K33
MGTHRXN1_129, K34
MGTHTXP1_129, J31
MGTHTXN1_129, J32
...
FMC F Clock Signals:
...
J21
(FMC F)
...
- B129_CLK0_P
- B129_CLK0_N
...
J21-D4
J21-D5
...
MGTREFCLK0P_129, L27
MGTREFCLK0N_129, L28
...
FMC F VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J21 (FMC F) | FMCF_3V3 | J21-D36 | DCDC U42, | Enable by SC CPLD U27, bank 2, pin Y10W19 |
3V3SB | J21-D32 | DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V_FMC_AF | J21-C35 | DCDC U51, | - | |
FMCAF_1V8 | J21-H40 | DCDC U39, | Enable by SC CPLD U27, bank 2, pin W19 | |
1V8' |
Table 6: FMC A Table 11: FMC F connector available VCC/VCCIO
FMC F A Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J21J10 (FMC FA) | M6M1 | Enable by SC CPLD U27, bank 2, pin W18Y19 | - |
Table 127: FMC F A connector cooling fan
B Anchor FMC
BF FMC F
FMC BF
FMC B F Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes | J4||||
---|---|---|---|---|---|---|---|---|---|---|
J21 (FMC | BF) | I/O | 241212 | 6 | Bank 47 44 HD | FMCBCFMCAF_1V8 | - | |||
2028 | 1014 | SC CPLD U27 Bank 48 HD1 | FMCBCFMCAF_1V8 | - | ||||||
2428 | 1214 | SC CPLD U27 Bank 49 HD3 | FMCBCFMCAF_1V8 | - | ||||||
I²C | 2 | - | I²C-Switch U13U37 | - | Muxed to MIO Bank 501 I²C Inteface | |||||
JTAG | 4 | - | SC CPLD U27 Bank 02 | 3.3VSB | - | |||||
MGT | - | 8 4 (4 2 x RX/TX) | Bank 130 129 GTH | - | 4x 2x MGT lanes | |||||
Clock Input | - | 2 | Bank 48 HD | - | 2x Reference clock inputs to PL bank | - | 1 | Bank 130 129 GTH | - | 1x Reference clock input to MGT bank |
Control Signals | 3 | - | SC CPLD U27 Bank 02 | 3.3VSB | 'FMCBFMCF_PG_C2M', 'FMCBFMCF_PG_M2C', 'FMCBFMCF_PRSNT' |
Table 138: FMC B F connector interfaces interface
FMC B F MGT Lanes:
FMC | MGT Lane | Bank | Type | Signal Schematic Name | FMC Connector Pin | FPGA Pin | J4|
---|---|---|---|---|---|---|---|
J21 (FMC | BF) | 30 | 130129 | GTH |
| J4J21-C6 | MGTHRXP3MGTHRXP0_130129, B33L31 |
21 | 130129 | GTH |
| J4J21-A2 | MGTHRXP2MGTHRXP1_130129, C31K33 | ||
1 | 130 | GTH |
| J4-A6 | MGTHRXP1_130, D33 | ||
0 | 130 | GTH |
| J4-A10 | MGTHRXP0_130, E31 |
...
FMC B Clock Signals:
...
J4
(FMC B)
...
- B130_CLK0_P
- B130_CLK0_N
...
J4-D4
J4-D5
...
MGTREFCLK0P_130, G27
MGTREFCLK0N_130, G28
...
- B_CLK0_M2C_P
- B_CLK0_M2C_N
...
J4-H4
J4-H5
...
IO_L6P_HDGC_48, F17
IO_L6N_HDGC_48, F18
...
- B_CLK1_M2C_P
- B_CLK1_M2C_N
...
J4-G2
J4-G3
...
IO_L5P_HDGC_48, G18
IO_L5N_HDGC_48, G19
...
129, J32 |
Table 9: FMC F connector MGT lanes
FMC F Clock Signals:
FMC | Signal Schematic Name | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J21 (FMC F) |
| 129 | J21-D4 | MGTREFCLK0P_129, L27 | Supplied by attached module |
Table 10: FMC F connector clock signal input
FMC F VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J21 (FMC F) | FMCF_3V3 | J21-D36 | DCDC U42, | Enable by SC CPLD U27, bank 2, pin Y10 |
3V3SB | J21-D32 | DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V_FMC_AF | J21-C35 | DCDC U51, | - | |
FMCAF_1V8 | J21-H40 | DCDC U39, | Enable by SC CPLD U27, bank 2, pin W19 |
Table 11: FMC F connector available VCC/VCCIO
FMC F Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J21 (FMC F) | M6 | Enable by SC CPLD U27, bank 2, pin W18 | - |
Table 12: FMC F connector cooling fan
Anchor FMC B FMC B
FMC B
FMC B Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J4 (FMC B) | I/O | 24 | 12 | Bank 47 HD | FMCBC_1V8 | - |
20 | 10 | Bank 48 |
...
FMC B VCC/VCCIO:
...
J4
(FMC B)
...
J4-D36
J4-D38
J4-D40
J4-C39
...
DCDC U33,
max. cur.: 5A
...
Enable by SC CPLD U27, bank 0, pin G11
Signal: 'EN_B_3V3'
...
J4-D32
...
DCDC U50,
...
J4-C35
J4-C37
...
DCDC U82,
max. cur.: 8A
...
not dedicated for FMC connectors
...
J4-H40
J4-G39
J4-F40
J4-E39
...
DCDC U40,
max. cur.: 5A
...
Enable by SC CPLD U27, bank 0, pin A3
Signal: 'EN_BC_1V8'
...
FMC B Cooling Fan:
...
J4
(FMC B)
...
Enable by SC CPLD U27, bank 0, pin A2
Signal: 'FAN_B_EN'
...
Table 17: FMC B connector cooling fan
...
FMC C
FMC C Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J8 (FMC C) | I/O | 20 | 10 | Bank 50 HD | FMCBC_1V8 | - |
6824 | 3412 | Bank 67 HP49 HD | FMCBC_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 20 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 230 130 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 50 48 HD | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 230 130 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 20 | 3.3VSB | 'FMCCFMCB_PG_C2M', 'FMCCFMCB_PG_M2C', 'FMCCFMCB_PRSNT' |
Table 1813: FMC C B connector interfaces
FMC C B MGT Lanes:
FMC | MGT Lane | Bank | Type | Signal Schematic Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J8J4 (FMC CB) | 3 | 230130 | GTH |
| J8J4-C6 | MGTHRXP3_230130, A4B33 |
2 | 230130 | GTH |
| J8J4-A2 | MGTHRXP2_230130, B2C31 | |
1 | 230130 | GTH |
| J8J4-A6 | MGTHRXP1_230130, C4D33 | |
0 | 230130 | GTH |
| J8J4-A10 | MGTHRXP0_230130, D2E31 |
Table 1914: FMC C B connector MGT lanes
FMC C B Clock Signals:
FMC | Signal Schematic Name | Bank | FMC Connector Pin | FPGA Pin | Notes | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
J8J4 (FMC CB) |
| 230130 | J8J4-D4 | MGTREFCLK0P_230130, C8G27 | Supplied by attached moduleC | |||||||
| C
| 50 48 HD | J8J4-H4 | J8J4-H5 | IO_ | L7PL6P_HDGC_ | 5048, | J12F17 | L7NL6N_HDGC_ | 5048, | H12F18 | Supplied by attached module |
| C
| 50 48 HD | J8J4-G2 | J8J4-G3 | IO_ | L8PL5P_HDGC_ | 5048, | H13G18 | L8NL5N_HDGC_ | 5048, | G13G19 | Supplied by attached module |
Table 2015: FMC C B connector clock signal input
FMC C B VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J8J4 (FMC CB) | FMCCFMCB_3V3 | J8J4-D36 | DCDC U34U33, | Enable by SC CPLD U27, bank 0, pin E11G11 |
3V3SB | J8J4-D32 | DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V | J8J4-C35 | DCDC U82, | not dedicated for FMC connectors | |
FMCBC_1V8 | J8J4-H40 | DCDC U40, | Enable by SC CPLD U27, bank 0, pin A3 |
Table 2116: FMC C B connector available VCC/VCCIO
FMC C B Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J8J4 (FMC CB) | M3M2 | Enable by SC CPLD U27, bank 0, pin B3A2 | - |
Table 2217: FMC C B connector cooling fan
D Anchor FMC
DC FMC C
FMC DC
FMC D C Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J7J8 (FMC DC) | I/O | 20 | 10 | Bank 65 HP50 HD | FMCDEFMCBC_1V8 | - |
48 | 24 | Bank 66 67 HP | FMCDEFMCBC_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 229 230 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 65 HP50 HD | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 229 230 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCDFMCC_PG_C2M', 'FMCDFMCC_PG_M2C', 'FMCDFMCC_PRSNT' |
Table 2318: FMC D C connector interfaces
FMC D C MGT Lanes:
FMC | MGT Lane | Bank | Type | Signal Schematic Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J7J8 (FMC DC) | 3 | 229230 | GTH |
| J7J8-C6 | MGTHRXP3_229230, F2A4 |
2 | 229230 | GTH |
| J7J8-A2 | MGTHRXP2_229230, H2B2 | |
1 | 229230 | GTH |
| J7J8-A6 | MGTHRXP1_229230, J4C4 | |
0 | 229230 | GTH |
| J7J8-A10 | MGTHRXP0_229230, K2D2 |
Table 2419: FMC D C connector MGT lanes
FMC D C Clock Signals:
FMC | Signal Schematic Name | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J7J8 (FMC DC) |
| 229230 | J7J8-D4 | MGTREFCLK0P_229230, G8C8 | Supplied by attached module |
| 65 HP50 HD | J7J8-H4 | IO_L14PL7P_T2L_N2_GC_65, AG5HDGC_50, J12 | Supplied by attached module | |
| 65 HP50 HD | J7J8-G2 | IO_L13PL8P_T2L_N0_GC_QBC_65, AE5HDGC_50, H13 | Supplied by attached module |
Table 2520: FMC D C connector clock signal input
FMC D C VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J7J8 (FMC DC) | FMCDFMCC_3V3 | J7J8-D36 | DCDC U35U34, | Enable by SC CPLD U27, bank 0, pin F8E11 |
3V3SB | J7J8-D32 | DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V | J7J8-C35 | DCDC U82, | not dedicated for FMC connectors | |
FMCDEFMCBC_1V8 | J7J8-H40 | DCDC U41U40, | Enable by SC CPLD U27, bank 0, pin C5A3 |
Table 2621: FMC D C connector available VCC/VCCIO
FMC D C Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J7J8 (FMC DC) | M4M3 | Enable by SC CPLD U27, bank 0, pin D7B3 | - |
Table 2722: FMC D C connector cooling fan
E Anchor FMC
ED FMC D
FMC ED
FMC E D Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J6J7 (FMC ED) | I/O | 2420 | 1210 | Bank 65 HP | FMCDE_1V8 | - |
4448 | 2224 | Bank 64 66 HP | FMCDE_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 228 229 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 64 HP65 HP | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 228 229 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCEFMCD_PG_C2M', 'FMCEFMCD_PG_M2C', 'FMCEFMCD_PRSNT' |
Table 2823: FMC E D connector interfaces
FMC E D MGT Lanes:
FMC | MGT Lane | Bank | Type | Signal Schematic Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J6J7 (FMC ED) | 3 | 228229 | GTH |
| J6J7-C6 | MGTHRXP3_228229, L4F2 |
2 | 228229 | GTH |
| J6J7-A2 | MGTHRXP2_228229, M2H2 | |
1 | 228229 | GTH |
| J6J7-A6 | MGTHRXP1_228229, P2J4 | |
0 | 228229 | GTH |
| J6J7-A10 | MGTHRXP0_228229, T2K2 |
Table 2924: FMC E D connector MGT lanes
FMC E D Clock Signals:
FMC | Signal Schematic Name | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J6J7 (FMC ED) |
| 228229 | J6J7-D4 | MGTREFCLK0P_228229, L8G8 | Supplied by attached module |
| 64 HP65 HP | J6J7-H4 | IO_L12PL14P_T1UT2L_N10N2_GC_6465, AL8AG5 | Supplied by attached module | |
| 64 HP65 HP | J6J7-G2 | IO_L11PL13P_T1UT2L_N8N0_GC_QBC_6465, AK8AE5 | Supplied by attached module |
Table 3025: FMC E D connector clock signal input
FMC E D VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J6J7 (FMC ED) | FMCEFMCD_3V3 | J6J7-D36 | DCDC U36U35, | Enable by SC CPLD U27, bank 0, pin E8F8 |
3V3SB | J6J7-D32 | DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V | J6J7-C35 | DCDC U82, | not dedicated for FMC connectors | |
FMCDE_1V8 | J6J7-H40 | DCDC U41, | Enable by SC CPLD U27, bank 0, pin C5 |
Table 3126: FMC E D connector available VCC/VCCIO
FMC E D Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J6J7 (FMC ED) | M5M4 | Enable by SC CPLD U27, bank 0, pin D6D7 | - |
Table 3227: FMC E D connector cooling fan
XMOD JTAG Interface
JTAG access to the Zynq MPSoC and SC CPLD is provided through XMOD header J24 and J35:
...
anchor | Figure_4 |
---|---|
title | Figure 4: XMOD header J24 and J35 |
...
Signal Assignment of XMOD header J24 and J35
...
Signal Schematic Name
...
XMOD Header
J24
...
- F_TCK
...
- F_TDI
...
- F_TDO
...
- F_TMS
...
GPIO/
UART
...
- XMOD2_A
...
- XMOD2_B
...
- XMOD2_E
...
- XMOD2_G
...
XMOD Header
J35
...
- C_TCK
...
- C_TDI
...
- C_TDO
...
- C_TMS
...
GPIO/
UART
...
- XMOD1_A
...
- XMOD1_B
...
- XMOD1_E
...
- XMOD1_G
...
Anchor FMC E FMC E
FMC E
FMC E Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J6 (FMC E) | I/O | 24 | 12 | Bank 65 HP | FMCDE_1V8 | - |
44 | 22 | Bank 64 HP | FMCDE_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 228 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 64 HP | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 228 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCE_PG_C2M', 'FMCE_PG_M2C', 'FMCE_PRSNT' |
Table 28: FMC E connector interfaces
FMC E MGT Lanes:
FMC | MGT Lane | Bank | Type | Signal Schematic Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J6 (FMC E) | 3 | 228 | GTH |
| J6-C6 | MGTHRXP3_228, L4 |
2 | 228 | GTH |
| J6-A2 | MGTHRXP2_228, M2 | |
1 | 228 | GTH |
| J6-A6 | MGTHRXP1_228, P2 | |
0 | 228 | GTH |
| J6-A10 | MGTHRXP0_228, T2 |
Table 29: FMC E connector MGT lanes
FMC E Clock Signals:
FMC | Signal Schematic Name | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J6 (FMC E) |
| 228 | J6-D4 | MGTREFCLK0P_228, L8 | Supplied by attached module |
| 64 HP | J6-H4 | IO_L12P_T1U_N10_GC_64, AL8 | Supplied by attached module | |
| 64 HP | J6-G2 | IO_L11P_T1U_N8_GC_64, AK8 | Supplied by attached module |
Table 30: FMC E connector clock signal input
FMC E VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J6 (FMC E) | FMCE_3V3 | J6-D36 | DCDC U36, | Enable by SC CPLD U27, bank 0, pin E8 |
3V3SB | J6-D32 | DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V | J6-C35 | DCDC U82, | not dedicated for FMC connectors | |
FMCDE_1V8 | J6-H40 | DCDC U41, | Enable by SC CPLD U27, bank 0, pin C5 |
Table 31: FMC E connector available VCC/VCCIO
FMC E Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J6 (FMC E) | M5 | Enable by SC CPLD U27, bank 0, pin D6 | - |
Table 32: FMC E connector cooling fan
XMOD JTAG Interface
JTAG access to the Zynq MPSoC and SC CPLD is provided through XMOD header J24 and J35:
Scroll Title | ||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||
|
Signal Assignment of XMOD header J24 and J35
Connector | Interface | Signal Schematic Name | XMOD Header Pin | Connected to | VCCIO | VCC |
---|---|---|---|---|---|---|
XMOD Header J24 | JTAG |
| J24-4 | Bank 503 PS Config, Pin R25 | PS_1V8 | 3V3SB |
| J24-10 | Bank 503 PS Config, Pin U25 | ||||
| J24-8 | Bank 503 PS Config, Pin T25 | ||||
| J24-12 | Bank 503 PS Config, Pin R24 | ||||
GPIO/ |
| J24-3 | SC CPLD U27, bank 5, Pin K7 | |||
| J24-7 | SC CPLD U27, bank 5, Pin K6 | ||||
| J24-9 | SC CPLD U27, bank 5, Pin H7 | ||||
| J24-11 | SC CPLD U27, bank 5, Pin H6 | ||||
XMOD Header J35 | JTAG |
| J35-4 | SC CPLD U27, bank 0, Pin A8 | 3V3SB | |
| J35-10 | SC CPLD U27, bank 0, Pin C7 | ||||
| J35-8 | SC CPLD U27, bank 0, Pin A6 | ||||
| J35-12 | SC CPLD U27, bank 0, Pin C9 | ||||
GPIO/ |
| J35-3 | SC CPLD U27, bank 0, Pin B19 | |||
| J35-9 | SC CPLD U27, bank 0, Pin A17 | ||||
| J35-7 | SC CPLD U27, bank 0, Pin C17 | ||||
| J35-11 | SC CPLD U27, bank 0, Pin A18 |
Table 33: XMOD interface signals
The JTAG interfaces of the TEB0911 UltraRack board can accessed with the XMOD-FT2232H adapter-board TE0790. The on-board devices Zynq MPSoC U1 and SC CPLD U27 can be programmed via USB2.0 interface of the TE0790 programmer.
XMOD-Header J24 is designated to program the Zynq Ultrascale+ MPSoC via USB interface, the 4 GPIO/UART pins (XMOD2_A/B/E/G) of this header are routed to the System Controller CPLD U27.
XMOD-Header J35 is designated to program the System Controller CPLD U27 via USB interface, the 4 GPIO/UART pins (XMOD1_A/B/E/G) of this header are also routed to the System Controller CPLD U27.
To program the System Controller CPLD, the JTAG interface of this devices have to be activated by DIP-switch S3-2. J35 JTAG is used for FMC JTAG, is JTAGENB is low (see CPLD Firmware).
When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO on both headers J24 and J35 will be sourced by the on-board supply voltages. Set the XMOD DIP-switch with the setting:
XMOD DIP-switches | Position |
---|---|
Switch 1 | ON |
Switch 2 | OFF |
Switch 3 | OFF |
Switch 4 | OFF |
Table 34: XMOD adapter board DIP-switch positions for voltage configuration
Note |
---|
Use Xilinx compatible TE0790 adapter board (designation TE-0790-xx without 'L') to program the Xilinx Zynq devices. The TE0790 adapter board's |
...
The JTAG interfaces of the TEB0911 UltraRack board can accessed with the XMOD-FT2232H adapter-board TE0790. The on-board devices Zynq MPSoC U1 and SC CPLD U27 can be programmed via USB2.0 interface of the TE0790 board.
XMOD-Header J24 is designated to program the Zynq Ultrascale+ MPSoC via USB interface, the 4 GPIO/UART pins (XMOD2_A/B/E/G) of this header are routed to the System Controller CPLD U27.
XMOD-Header J35 is designated to program the System Controller CPLD U27 via USB interface, the 4 GPIO/UART pins (XMOD1_A/B/E/G) of this header are also routed to the System Controller CPLD U27.
To program the System Controller CPLD, the JTAG interface of this devices have to be activated by DIP-switch S3-2.
When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO on both headers J24 and J35 will be sourced by the on-board supply voltages. Set the XMOD DIP-switch with the setting:
...
Table 34: XMOD adapter board DIP-switch positions for voltage configuration
Note |
---|
Use Xilinx compatible TE0790 adapter board (designation TE-0790-xx with out 'L') to program the Xilinx Zynq devices. The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download. |
...
Scroll Title | ||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||
| 1 |
|
Scroll Only |
---|
Following table describes the signals and control lines of the Gigabit Ethernet interface of the board:
PHY Pin | Connected to | Notes |
---|---|---|
MDC/MDIO | PS bank 502 MIO76, MIO77 | - |
PHY LED0..2 | SC CPLD U27, bank 4, pin L5, L1, K1 | see schematic for details, forwarded to RJ45 GbE MagJack J7 |
PHY_CLK125M | SC CPLD U27, bank 4, pin K2 | 125 MHz Ethernet PHY clock out |
CONFIG | pulled up to PS_1V8 | Configuration of PHY address LSB and VDDO level |
RESETn | SC CPLD U27, bank 4, pin L6 | Active low reset line |
RGMII | PS bank 502 MIO64 ... MIO75 | Reduced Gigabit Media Independent Interface |
SGMII | - | Serial Gigabit Media Independent Interface |
MDI | RJ45 GbE MagJack J13 | Media Dependent Interface |
...
Scroll Title | ||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||
|
The 4-port USB3 hub is connected to the Zynq MPSoC's PS GTR bank, the USB2 PHY is connected to the PS MIO bank 502:
...
Scroll Title | |||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||||||||||||||||||||||||
|
Connector | Interface | Signal Schematic Name | Connected to | Logic | Notes |
---|---|---|---|---|---|
SFP+ J9A | MGT Lane |
| MGTHTXP3_129, G31 | TX: Output RX: Input | Multi gigabit highspeed data lane |
I²C |
| 8-channel I²C-switch U37 | BiDir | 2-wire Serial Interface | |
Control Lines |
| I²C 8-bit I/O Port-Expander U86 | Output, low active | Full RX bandwidth | |
| Output, low active | Reduced RX bandwidth | |||
| Input, low active | Module present / not present | |||
| Input, high active | Fault / Normal Operation | |||
| SC CPLD U27, bank 2, pin V8 | Input, high active | Loss of receiver signal | ||
| SC CPLD U27, bank 2, pin Y7 | Output, low active | SFP Enabled / Disabled | ||
SFP+ J9B | MGT Lane |
| MGTHTXP2_129, H29 | TX: Output RX: Input | Multi gigabit highspeed |
I²C |
| 8-channel I²C-switch U37 | Bidir | 2-wire Serial Interface | |
Control Lines |
| I²C 8-bit I/O Port-Expander U86 | Output, low active | Full RX bandwidth | |
| Output, low active | Reduced RX bandwidth | |||
| Input, low active | Module present / not present | |||
| Input, high active | Fault / Normal Operation | |||
| SC CPLD U27, bank 2, pin W7 | Input, high active | Loss of receiver signal | ||
| SC CPLD U27, bank 2, pin V7 | Output. low active | SFP Enabled / Disabled |
...
Scroll Title | ||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||
|
Connector | Interface | Signal Schematic Name | Connected to | Notes |
---|---|---|---|---|
M.2-NGFF PCIe Socket U2 | MGT Lane |
| PS_MGTRTXP0_505, AB29 | Multi gigabit highspeed TX: Output RX: Input |
Clock Input |
| Quad programmable PLL clock generator U12, CLK0 | Reference clock signal | |
Control Lines |
| SC CPLD U27, bank 2, pin AA13 | LED, Output, High active | |
| SC CPLD U27, bank 2, pin AA12 | PCIe sleep state, Input, Low active | ||
| SC CPLD U27, bank 2, pin AA11 | PCIe reset input, Input, Low active | ||
| SC CPLD U27, bank 2, pin AB11 | PCIe Link reactivation, Input, Low active | ||
| connect to GND | PCIe Clock Request, Low active |
...
Scroll Title | ||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||
|
Follwowing table contains a brief description of the MGT lanes and control and status signals of the DisplayPort interface:
...
Scroll Title | |||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||||||||||||||||||||||
|
Following table gives an overview about the I/O signals of the DDR4 SDRAM memory interface:
Connector | DDR4 SDRAM I/O Signal | Signal Schematic Name | Connected to | Notes |
---|---|---|---|---|
DDR4 SO-DIMM Socket U13 | Address inputs |
| PS DDR Bank 504 | - |
Bank address inputs |
| - | ||
Bank group inputs |
| - | ||
Differential clocks |
| 2 x DDR4 clock | ||
Data input/output |
| - | ||
Check bit input/output |
| - | ||
Data strobe (differential) |
| - | ||
Data mask and data bus inversion |
| - | ||
Serial address inputs |
| address range configuration on I²C bus | ||
Control Signals |
| chip selest signal | ||
| On-die termination enable | |||
| nRESET | |||
| Command and address parity input | |||
| Clock enable | |||
| CRC error flag | |||
| Activation command input | |||
| Temperature event | |||
I²C |
| 8-channel I²C switch U37 | - |
Table 40: DDR4 64-bit memory interface signals and pins
Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s, which also depends on the used SO-DIMM module.
...
Scroll Title | ||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||
|
The CAN interface of external devices can be connected via D-SUB 9-pin male connector J3 or to the 6-pin male header J15:
Connector | Signal Schematic Name | Connected to | Notes |
---|---|---|---|
D-SUB 9-pin J3 |
| CAN Transceiver U48, pin 7 | - |
| CAN Transceiver U48, pin 6 | - | |
6-pin male header J15 |
| CAN Transceiver U48, pin 7 | - |
| CAN Transceiver U48, pin 6 | - | |
CAN Transceiver | Signal Schematic Name | Connected to | Notes |
TCAN337 U48 |
| SC CPLD U27, bank 0, pin C16 | 3.3V VCCIO |
| SC CPLD U27, bank 0, pin B15 | 3.3V VCCIO | |
| SC CPLD U27, bank 0, pin C15 | 3.3V VCCIO | |
| SC CPLD U27, bank 0, pin D15 | 3.3V VCCIO |
Table 41: CAN interface signals and pins
SD Card Interface
The SD Card interface of the TEB0911 board is routed via SD IO interface to the PS MIO bank 501 of the Zynq Ultrascale+ MPSoC (3.3V VCCO). The SC CPLD U27 controls the load switch Q3 to enable the card sockets J11 with signal 'SD_EN', bank 2, pin U11. The "Card Detect" and "Write Protect" signal are also routed to the SC CPLD:
Scroll Title | |||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||||||||||||||||||||
|
The SD Card socket have following signal and pin assignment:
Connector | Signal Schematic Name | Connected to | Notes |
---|---|---|---|
SD Card Socket J11 |
| PS bank 501 Pins: MIO46 ... MIO51 | - |
| - | ||
| - | ||
| - | ||
| - | ||
| - | ||
| SC CPLD U27, bank 2, pin T11 | Card Detect | |
| SC CPLD U27, bank 2, pin T10 | Write Protect |
...
Scroll Title | ||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||
|
Following table contains a brief description of the control signals of the fan connectors:
Connector | Signal Schematic Name | Connected to | Notes |
---|---|---|---|
Fan Connector J2 |
| SC CPLD U27, bank 0, pin E10 | -PWM signal to fan |
| SC CPLD U27, bank 0, pin D11 | -sense RPM signal of fan | |
| SC CPLD U27, bank 0, pin C8 | Controls 12V Load Switchenable 12V fan supply voltage | |
Fan Connector J23 |
| SC CPLD U27, bank 0, pin D9 | -PWM signal to fan |
| SC CPLD U27, bank 0, pin G12 | -sense RPM signal of fan | |
| SC CPLD U27, bank 0, pin B4 | Controls 12V Load Switchenable 12V fan supply voltage | |
Fan Connector J33 |
| SC CPLD U27, bank 0, pin B13 | -PWM signal to fan |
| SC CPLD U27, bank 0, pin A13 | -sense RPM signal of fan | |
| SC CPLD U27, bank 0, pin A12 | Controls 12V Load Switchenable 12V fan supply voltage |
Table 43: 4-wire PWM fan connectors signals and pins
...
Scroll Title | |||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||||||||||||||||||||
|
Connector | Signal Schematic Name | Connected to | Notes |
---|---|---|---|
Pin Header J22 |
| clock generator U17, pin 16 | PS_1V8 VCCIO |
| clock generator U17, pin 18 | ||
SMA Coax J25 |
| clock generator U17, pin 1 | - |
Table 44: Clock generator Si5345A external interfaces
On-board Peripherals
HTML |
---|
<!-- Components on the Module, like Flash, PLL, PHY... --> |
...
Scroll Title | |||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||||||||||||||||||||
|
For detailed information about the current function of the MIO-pin in conjunction with the SC CPLD, the internal signal assignment and implemented logic, refer to the Wiki reference page of the SC CPLD firmware of this board or into the bitstream file of the SC CPLD.
...
Table 46: MIO-pin assignment of the module's I2C interface
Info |
---|
The I²C switches can be reseted simultanously by the pin 'I2C_RST', which is connected to SC CPLD U27, bank 4 pin L2 with low active logic. |
I2C addresses (7 bit without read/write-bit) for on-board slave devices are listed in the table below:
...
The TEB0911 carrier board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip and all have I²C interfaces, the I²C interfaces of the EEPROM's are multiplexed to the I²C switch U37:
EEPROM Modell | Designator | Memory Density | Purpose |
---|---|---|---|
24LC128-I/ST | U57 | 128 Kbit | user |
24AA025E48T-I/OT | U60 | 2 Kbit | user |
24AA025E48T-I/OT | U45 | 2 Kbit | user |
24AA025E48T-I/OT | U83 | 2 Kbit | user |
24LC128-I/ST | U5 | 128 Kbit | USB3 Hub U4 configuration memory |
Table 47: On-board configuration EEPROMs overview
CAN FD Transceiver
On-board CAN FD (Flexible Data Rate) transceiver U48 is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.
The transceiver is connected to System Controller CPLD U27, means it works on this interface with 3.3V VCCIO. The logical signal processing of the CAN interface depends on the current firmware ot the SC CPLD.
On-board Flash Memory
On-board QSPI flash memory U24 and U25 on the TEB0911 board is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity each. The QSPI Flash memory ICs are connected to the PS MIO bank (Dual QSPI MIO0 ... MIO12) of the Zynq Ultrascale+ MPSoC. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the Zynq MPSoC allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
The TEB0911 board is also equipped with embedded MMC memory connected to the PS MIO bank (MIO13 ... MIO23) of the Zynq Ultrascale+ MPSoC. The memory is provided by MTFC4GACAJCN-4M IT from Micron Technology. It has a memory density of 32 Gbit (4 GByte) and is sectored into 8 banks a 4 Gbit.
...
dual parallel booting possible, 64 MByte total QSPI Flash memory
connected via Dual QSPI MIO0 ... MIO12
...
Quad SPI Flash memory ICs U24 and U25 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.
eMMC Flash memory IC U25 is connected to Zynq MPSoC by pins MIO13 ... MIO23.
...
- MIO0
...
- MIO7
...
- MMC-D0
...
- MIO1
...
- MIO8
...
- MMC-D1
...
- MIO2
...
- MIO9
...
- MMC-D2
...
- MIO3
...
- MIO10
...
- MMC-D3
...
- MIO4
...
- MIO11
...
- MMC-D4
...
- MIO5
...
- MIO12
...
- MMC-D5
...
- MMC-D6
...
- MMC-D7
...
- MMC-CMD
...
- MMC-CLKR
...
- MM_ RST
...
Note |
---|
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
Oscillators
The TEB0911 board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:
...
- PS_CLK
...
- USB_CLK
...
- XAXB_P
- XAXB_N
...
- ETH_CLKIN
...
SiTime SiT8008AI oscillator, U87
optional, not equipped
...
- CLK_SC
...
- IN0_P
...
DSC1123 oscillator, U92
optional, not equipped
...
- B505_CLK3_P
- B505_CLK3_N
...
-I/ST | U5 | 128 Kbit | USB3 Hub U4 configuration memory |
Table 47: On-board configuration EEPROMs overview
CAN FD Transceiver
On-board CAN FD (Flexible Data Rate) transceiver U48 is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.
The transceiver is connected to System Controller CPLD U27, means it works on this interface with 3.3V VCCIO. The logical signal processing of the CAN interface depends on the current firmware ot the SC CPLD.
On-board Flash Memory
On-board QSPI flash memory U24 and U25 on the TEB0911 board is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity each. The QSPI Flash memory ICs are connected to the PS MIO bank (Dual QSPI MIO0 ... MIO12) of the Zynq Ultrascale+ MPSoC. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the Zynq MPSoC allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
The TEB0911 board is also equipped with embedded MMC memory connected to the PS MIO bank (MIO13 ... MIO23) of the Zynq Ultrascale+ MPSoC. The memory is provided by MTFC4GACAJCN-4M IT from Micron Technology. It has a memory density of 32 Gbit (4 GByte) and is sectored into 8 banks a 4 Gbit.
IC | Name | Memory Density | Connected to | Notes |
---|---|---|---|---|
QSPI Flash U24 | N25Q256A11E1240E | 256 Mbit (32 MByte) | QSPI0: MIO0 ... MIO5 | dual parallel booting possible, 64 MByte total QSPI Flash memory connected via Dual QSPI MIO0 ... MIO12 |
QSPI Flash U25 | N25Q256A11E1240E | 256 Mbit (32 MByte) | QSPI0: MIO7 ... MIO12 | |
eMMC Flash U26 | MTFC4GACAJCN-4M IT | 32 Gbit (4 GByte) | SD0 eMMC: MIO13 ... MIO23 | bootable eMMC |
Table 48: On-board Flash memory ICs overview
Quad SPI Flash memory ICs U24 and U25 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.
eMMC Flash memory IC U25 is connected to Zynq MPSoC by pins MIO13 ... MIO23.
MIO | Signal Schematic Name | Flash U24 Pin | MIO | Signal Schematic Name | Flash U25 Pin | MIO | Signal Schematic Name | Flash U26 Pin | ||
---|---|---|---|---|---|---|---|---|---|---|
0 |
| B2 | 7 |
| C2 | 13 |
| H3 | ||
1 |
| D2 | 8 |
| D3 | 14 |
| H4 | ||
2 |
| C4 | 9 |
| D2 | 15 |
| H5 | ||
3 |
| D4 | 10 |
| C4 | 16 |
| J2 | ||
4 |
| D3 | 11 |
| D4 | 17 |
| J3 | ||
5 |
| C2 | 12 |
| B2 | 18 |
| J4 | ||
19 |
| J5 | ||||||||
20 |
| J6 | ||||||||
21 |
| W5 | ||||||||
22 |
| W6 | ||||||||
23 |
| U5 |
Table 49: PS MIO pin assignment of the Flash memory ICs
Note |
---|
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
Oscillators
The TEB0911 board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:
Clock Source | Signal Schematic Name | Frequency | Clock Input Destination |
---|---|---|---|
SiTime SiT8008BI oscillator, U22 |
| 33.333333 MHz | Zynq MPSoC PS Config Bank 503, pin U24 |
SiTime SiT8008AI oscillator, U16 |
| 52.000000 MHz | USB2 transceiver PHY U15, pin 26 |
Kyocera CX3225SB26000, Y3 | - | 26.000 MHz | 4-port USB3 Hub U4, pin 68/69 |
Kyocera CX3225SB26000, Y2 |
| 54.000 MHz | PLL clock generator U17, pin 8/9 |
SiTime SiT8008BI oscillator, U21 |
| 25.000000 MHz | Gigabit Ethernet PHY U20, pin 34 |
SiTime SiT8008AI oscillator, U87 optional, not equipped |
| 25.000000 MHz | System Controller CPLD U27, bank 2, pin AA9 |
SiTime SiT8008BI oscillator, U18 |
| 25.000000 MHz | PLL clock generator U17, pin 63 |
SiTime SiT8008AI oscillator, U85 | - | 25.000000 MHz | PLL clock generator U12, pin 3 |
DSC1123 oscillator, U92 optional, not equipped |
| 100.0000 MHz | PS GTR Bank 505 Lane 3, dedicated for DisplayPort, pin U31, U32 |
Table 50: Reference clock signal oscillators
Programmable Clock Generator Si5338A
There is a Si5338A U12, Silicon Labs I2C programmable quad PLL clock generator on-board to generate various reference clocks for the Zynq MPSoC MGT banks and on-board peripherals.
Si5338A Pin | Signal Schematic Name | Connected to | Clock Direction | Note |
---|---|---|---|---|
IN1 |
| U17, pin 54 | Input | Differential reference clock input from PLL clock generator U17 |
IN2 |
| U17, pin 53 | Input | |
IN3 | - | U85, pin 3 | Input | 25.000000 MHz oscillator, Si8008AI |
IN4 | - | GND | Input | LSB (pin 'IN4') of the default I²C-adress 0x70 not set |
IN5 | - | Not connected | Input | Not used |
IN6 | - | GND | Input | Not used |
CLK0A |
| U2, pin 55 | Output | NGFF M.2 PCIe socket (Key M), |
CLK0B |
| U2, pin 53 | Output | |
CLK1A |
| U1, pin U27 | Output | PS GTR Bank 505 Lane 2 |
CLK1B |
| U1, pin U28 | Output | |
CLK2A |
| U1, pin W27 | Output | PS GTR Bank 505 Lane 1 |
CLK2B |
| U1, pin W28 | Output | |
CLK3A |
| U1, pin AA27 | Output | PS GTR Bank 505 Lane 0 |
CLK3B |
| U1, pin AA28 | Output |
Table 51: Programmable quad PLL clock generator inputs and outputs
Programmable Clock Generator Si5345A
Following table shows on-board Silicon Labs I2C programmable Si5345A U17 10-output programmable PLL reference clock generator inputs and outputs:
Si5345A |
---|
Table 50: Reference clock signal oscillators
Programmable Clock Generator Si5338A
There is a Si5338A U12, Silicon Labs I2C programmable quad PLL clock generator on-board to generate various reference clocks for the Zynq MPSoC MGT banks and on-board peripherals.
Si5338A Pin | Signal Schematic Name | Connected to | Clock Direction | Note |
---|---|---|---|---|
IN0 |
| not connected | Input | Not used |
| GND | |||
IN1 |
| U17SMA Coax J25, pin 541 | Input | Differential external reference clock input from PLL clock generator U17 |
IN2 |
| U17, pin 53 | Input | |
IN3 | - | U85, pin 3 | Input | 25.000000 MHz oscillator, Si8008AI |
IN4 | - | GND | Input | LSB (pin 'IN4') of the default I²C-adress 0x70 not set |
IN5 | - | Not connected | Input | Not used |
IN6 | - | GND | Input | Not used |
CLK0A |
| U2, pin 55 | Output | NGFF M.2 PCIe socket (Key M), |
CLK0B |
| U2, pin 53 | Output | |
CLK1A |
| U1, pin U27 | Output | PS GTR Bank 505 Lane 2, dedicated for DisplayPort, |
CLK1B |
| U1, pin U28 | Output | |
CLK2A |
| U1, pin W27 | Output | PS GTR Bank 505 Lane 1, dedicated for USB3 interface |
CLK2B |
| U1, pin W28 | Output | |
CLK3A |
| U1, pin AA27 | Output | PS GTR Bank 505 Lane 0, dedicated for SSD interface |
CLK3B |
| U1, pin AA28 | Output |
Table 51: Programmable quad PLL clock generator inputs and outputs
Programmable Clock Generator Si5345A
Following table shows on-board Silicon Labs I2C programmable Si5345A U17 10-output programmable PLL reference clock generator inputs and outputs:
...
- IN0_P
...
- IN0_N
...
- IN1_P
...
- IN1_N
...
-
...
-
...
not used
...
- CLK0_P
...
not used
...
- CLK0_N
...
- CLK1_P
...
GTH bank 229 reference clock input
...
- CLK1_N
...
- CLK2_P
...
GTH bank 230 reference clock input
...
- CLK2_N
...
- CLK3_P
...
- CLK3_N
...
- CLK4_P
...
- CLK4_N
...
- CLK5_P
...
- CLK5_N
...
- CLK6_P
...
- CLK6_N
...
- CLK7_P
...
- CLK7_N
...
- CLK8_P
...
Differential reference clock input to
PLL clock generator U12
...
- CLK8_N
...
- XAXB_P
...
- XAXB_N
Table 52: Programmable 10-output PLL clock generator inputs and outputs
Info |
---|
The PLL clock generator U17 can be reseted by the low active pin 'PLL_RST' connected to SC CPLD U27, bank 4, pin L4. |
On-board LEDs
The TEB0911 board is equipped with several LEDs to signal current states and activities.
...
Reflects inverted DONE signal. ON when FPGA is not configured,
OFF as soon as PL configuration is finished.
...
LED is on if all USB3 and USB2 ports are in the suspend state and is
off when one of the ports comes out of the suspend state.
...
functionality depends on the current firmware of the SC CPLD U27
refer to the documentation
section: LED
...
Table 53: On-board LEDs
User Buttons
There are two switch buttons available to the user connected to the SC CPLD U27:
...
high active logic, connected to 3V3SB,
functionality depends on the current firmware of the SC CPLD U27
refer to the documentation
...
| GND | |||
IN2 | - | not connected | Input | not used |
- | not connected | |||
IN3 | - | not connected | Input | not used |
- | not connected | |||
OUT0 |
| not connected | Output | not used |
| not connected | |||
OUT1 |
| U1, pin E8 | Output | GTH bank 229 reference clock input |
| U1, pin E7 | |||
OUT2 |
| U1, pin B10 | Output | GTH bank 230 reference clock input |
| U1, pin B9 | |||
OUT3 |
| U1, pin J8 | Output | GTH bank 228 reference clock input |
| U1, pin J7 | |||
OUT4 |
| U1, pin N27 | Output | GTH bank 128 reference clock input |
| U1, pin N28 | |||
OUT5 |
| U1, pin J27 | Output | GTH bank 129 reference clock input |
| U1, pin J28 | |||
OUT6 |
| U1, pin E27 | Output | GTH bank 130 reference clock input |
| U1, pin E28 | |||
OUT7 |
| U27, pin E1 | Output | Clock signal input to SC CPLD, bank 5 |
| not connected | |||
OUT8 |
| U12, pin 2 | Output | Differential reference clock input to |
| U12, pin 1 | |||
OUT9 | - | not connected | Output | not used |
- | not connected | |||
XA/XB |
| 54.000 MHz quartz oscillator Y1 | Input | Differential quartz oscillator clock input |
|
Table 52: Programmable 10-output PLL clock generator inputs and outputs
Info |
---|
The PLL clock generator U17 can be resetted by the low active pin 'PLL_RST' connected to SC CPLD U27, bank 4, pin L4. The on-board header J22 provides the possibility to program the clock generator U17 via I²C bus (1.8V reference voltage). |
On-board LEDs
The TEB0911 board is equipped with several LEDs to signal current states and activities.
LED | Color | Connected to | Description and Notes |
---|---|---|---|
D6 | red | Zynq MPSoC U1, pin W21 | Reflects inverted DONE signal. ON when FPGA is not configured, |
D17 | green | USB3 Hub U4, pin 25 | LED is on if all USB3 and USB2 ports are in the suspend state and is |
D18 | green | USB3 Hub U4, pin 4 | LED output for downstream 1 port. |
D19 | green | USB3 Hub U4, pin 63 | LED output for downstream 3 port. |
D2 | red | SC CPLD U27, bank 2, pin AB17 | SFP+ interface status. The LEDs are fitted on-board under the SFP+ connector cage. |
D4 | green | SC CPLD U27, bank 2, pin AB18 | |
D3 | red | SC CPLD U27, bank 2, pin AA16 | |
D5 | green | SC CPLD U27, bank 2, pin AB15 | |
D13 | green | SC CPLD U27, bank 2, pin U12 | functionality depends on the current firmware of the SC CPLD U27 refer to the documentation section: LED |
D14 | green | SC CPLD U27, bank 2, pin V12 | |
D15 | green | SC CPLD U27, bank 2, pin W12 | |
D16 | red | SC CPLD U27, bank 2, pin V13 |
Table 53: On-board LEDs
User Buttons
There are two switch buttons available to the user connected to the SC CPLD U27:
Button | Connected to | Notes |
---|---|---|
S1 | SC CPLD U27, bank 0, pin F13 | high active logic, connected to 3V3SB, functionality depends on the current firmware of the SC CPLD U27 |
S2 | SC CPLD U27, bank 0, pin G13 |
Table 54: On-board switch buttons
Configuration DIP-switches
There are two 4-bit DIP-witches S3 and S4 present on the TEB0911 board to configure options and set parameters. The following section describes the functionalities of the particular switches.
Table below describes the functionalities of the switches of DIP-switches S3 and S4 at their each positions:
DIP-switch S3 | Signal Schematic Name | Connected to | Functionality | Notes |
---|---|---|---|---|
S3-1 |
| Zynq MPSoC U1, pin AD15 | Positions ON: PUDC_B is Low OFF: PUDC_B is HIGH | Internal pull-up resistors during configuration are enabled at ON-position,means I/O's are 3-stated until configuration of the FPGA completes. |
S3-2 |
| SC CPLD U27, bank 0, pin A16 | Positions | JTAG interface of the SC CPLD, accessible on XMOD header J35 |
S3-3 |
| SC CPLD U27, bank 0, pin E17 | set 2-bit code for boot mode selection | TEB0911 CPLD Firmware Documentation Section: Boot Mode |
S3-4 |
| SC CPLD U27, bank 0, pin D16 | ||
DIP-switch S4 | Signal Schematic Name | Connected to | Functionality | Notes |
S4-1 |
| SC CPLD U27, bank 0, pin D18 | user defined | For functionalities of these switches in the current CPLD firmware, refer to the TEB0911 CPLD Firmware Documentation. |
S4-2 |
| SC CPLD U27, bank 0, pin D16 | ||
S4-3 |
| SC CPLD U27, bank 0, pin C19 | ||
S4-4 |
| SC CPLD U27, bank 0, pin C18 |
Table 55: DIP-switch S3 and S4 functionality description
Power and Power-On Sequence
HTML |
---|
<!--
If power sequencing and distribution is not so much, you can join both sub sections together
--> |
Power Consumption
The maximum power consumption of the board mainly depends on the design running on the FPGA.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
Power Input | Typical Current |
---|---|
24V VIN | TBD* |
Table 56: Typical power consumption, *to Be Determined soon with reference design setup.
Power supply with minimum current capability of 2A for system startup is recommended. If using all FMC connectors with FPGA Mezzanine Cards, a higher current availability of up to 4A is recommended.
The TEB0911 UltraRack board is equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.
This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq UltraScale+ MPSoC has multiple power domains, whereby each power domain requires its own particular on-board DC-DC converters.
The Processing System contains three Power Domains:
- Battery Power Domain (BBRAM and RTC)
- Full-Power Domain (Application Processing Unit, DDR Controller, Graphics Processing Unit and High-Speed Connectivity)
- Low-Power Domain (Real-Time Processing Unit, Security and Configuration Unit, Platform Management Unit, System Monitor and General Connectivity)
- Programmable Logic (PL)
Power Distribution Dependencies
There are following dependencies how the initial 24V voltage from the main power jack J34 is distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:
Scroll Title | ||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||
|
Power distribution to the MPSoC PS and PL units:
Scroll Title | ||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||
|
Info |
---|
Note: The DC-DC converter U91 LTM4630EY has an integrated temperature diode for device temperature monitoring. The analog signal 'TEMP_CORE_DC' on pin J6 of the converter is routed to the dedicated differential analog interface (XADC) of the Zynq MPSoC, pin U18 (V_P), pin V17 (V_N) is connected to analog GND. |
Warning |
---|
To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
Power-On Sequence
The TEB0911 UltraRack board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.
On the TEB0911 UltraRack board following Power Domains will be powered up in a certain sequence with by enable and power-good signals of the DC-DC converters, which are controlled by the System Controller CPLD U27:
- Low-Power Domain (LPD)
- Programmable Logic (PL) and Full-Power Domain (FPD)
- GTH, PS GTR transceiver and DDR memory
Hence, those three power instances will be powered up consecutively when the Power-Good signals of the previous instance is asserted.
Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter control signals (Enable, Power-Good), which will power-up in descending order as listed in the blocks of the diagram.
Scroll Title | ||||
---|---|---|---|---|
| ||||
|
Table 54: On-board switch buttons
Configuration DIP-switches
There are two 4-bit DIP-witches S3 and S4 present on the TEB0911 board to configure options and set parameters. The following section describes the functionalities of the particular switches.
Table below describes the functionalities of the switches of DIP-switches S3 and S4 at their each positions:
...
- PUDC_B
...
- JTAGENB
...
Positions
ON: SC CPLD's JTAG enabled
OFF: SC CPLD's JTAG disabled
...
- SC_SW1
...
TEB0911 CPLD Firmware Documentation
Section: Boot Mode
...
- SC_SW2
...
- U_SW1
...
- U_SW2
...
- U_SW3
...
- U_SW4
...
Table 55: DIP-switch S3 and S4 functionality description
Power and Power-On Sequence
HTML |
---|
<!--
If power sequencing and distribution is not so much, you can join both sub sections together
--> |
Power Consumption
The maximum power consumption of the board mainly depends on the design running on the FPGA.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
...
Power supply with minimum current capability of 2A for system startup is recommended. If using all FMC connectors with FPGA Mezzanine Cards, a higher current availability of up to 4A is recommended.
The TEB0911 UltraRack board is equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.
This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq UltraScale+ MPSoC has multiple power domains, whereby each power domain requires its own particular on-board DC-DC converters.
The Processing System contains three Power Domains:
- Battery Power Domain (BBRAM and RTC)
- Full-Power Domain (Application Processing Unit, DDR Controller, Graphics Processing Unit and High-Speed Connectivity)
- Low-Power Domain (Real-Time Processing Unit, Security and Configuration Unit, Platform Management Unit, System Monitor and General Connectivity)
- Programmable Logic (PL)
Power Distribution Dependencies
There are following dependencies how the initial 24V voltage from the main power jack J34 is distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:
...
anchor | Figure_16 |
---|---|
title | Figure 16: Power distribution diagram |
...
Power distribution to the MPSoC PS and PL units:
Scroll Title | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
anchor | Figure_17 | title | Figure 17: Power distribution diagram continued
| 3 |
Warning |
---|
To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
Info |
---|
Note: The DC-DC converter U91 LTM4630EY has an integrated temperature diode for device temperature monitoring. The analog signal 'TEMP_CORE_DC' on pin J6 of the converter is routed to the dedicated differential analog interface (XADC) of the Zynq MPSoC, pin U18 (V_P), pin V17 (V_N) is connected to analog GND. |
Power-On Sequence
The TEB0911 UltraRack board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.
On the TEB0911 UltraRack board following Power Domains will be powered up in a certain sequence with by enable and power-good signals of the DC-DC converters, which are controlled by the System Controller CPLD U27:
- Low-Power Domain (LPD)
- Programmable Logic (PL) and Full-Power Domain (FPD)
- GTH, PS GTR transceiver and DDR memory
Hence, those three power instances will be powered up consecutively when the Power-Good signals of the previous instance is asserted.
Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter control signals (Enable, Power-Good), which will power-up in descending order as listed in the blocks of the diagram.
...
anchor | Figure_18 |
---|---|
title | Figure 18: Power-On sequence diagram |
|
Power Rails
Peripheral Designator | VCC / VCCIO Schematic Name | Voltage | Direction | Pins | Notes |
---|---|---|---|---|---|
J12 | DP_TX_PWR | 3.3V | Out | Pin 20 | Display-Port Connector |
J9A | SFP_SSD | 3.3V | Out | Pin T15, T16 | SFP+ 2x1 Connector |
J9B | SFP_SSD | 3.3V | Out | Pin L15, L16 | |
J13A | VBUS1 | 5.0V | Out | Pin U1 | USB3 Ports |
J13B | VBUS2 | 5.0V | Out | Pin U10 | |
J11 | - | 3.3V | Out | Pin 4 | MicroSD Card Socket |
B1 | PSBATT | 3.0V | In | Pin + | Battery Holder CR1220 |
U2 | SSD1_3V3_1 | 3.3V | Out | Pin 2, 4 | SSD PCIe connector |
SSD1_3V3_2 | 3.3V | Out | Pin 70, 72, 74 | ||
SSD1_3V3_3 | 3.3V | Out | Pin 12, 14, 16, 18 | ||
U3 | DDR_1V2 | 1.2V | Out | Pin 111, 112, 117, 118, 123, 124, 129, 130, 135, 136, 141, 142, 147, 148, 153, 154, 159, 160, 163 | DDR4 SO-DIMM socket |
VPP_SPD | 2.5V | Out | Pin 255, 257, 259 |
Table 57: Power pin description of peripherals' connectors
XMOD / JTAG Designator | VCC / VCCIO Schematic Name | Voltage | Direction | Pins | Notes |
---|---|---|---|---|---|
J24 | 3V3SB | 3.3V | Out | Pin 5 | Zynq MPSoC JTAG |
PS_1V8 | 1.8V | Out | Pin 6 | ||
J35 | 3V3SB | 3.3V | Out | Pin 5, 6 | SC CPLD JTAG |
Table 58: Power pin description of XMOD/JTAG Connector
Main Power |
---|
...
Power Rails
Peripheral Designator | VCC / VCCIO Schematic Name | Voltage | Direction | Pins | Notes |
---|---|---|---|---|---|
J12J1 | DP PWR_ TXIN_ PWR24V | 3.3V 24V | OutIn | Pin 20 | Display-Port Connector |
J9A | SFP_SSD | 3.3V | Out | Pin T15, T16 | SFP+ 2x1 Connector |
J9B | SFP_SSD | 3.3V | Out | Pin L15, L16 | |
J13A | VBUS1 | 5.0V | Out | Pin U1 | USB3 Ports |
J13B | VBUS2 | 5.0V | Out | Pin U10 | |
2, 4 | 24V Power Jack |
Table 59: Power pin description of main power supply connector
FMC Designator | VCC / VCCIO Schematic Name | Voltage | Direction | Pins | Notes | |
---|---|---|---|---|---|---|
J10 | 12V_FMC_AF | 12.0V | Out | Pin C35, C37 | - | |
3V3VSB | 3.3V | Out | Pin D32 | - | ||
FMCA_3V3 | J11 | - | 3.3V | Out | Pin 4 | MicroSD Card Socket |
B1 | PSBATT | 3.0V | In | Pin + | Battery Holder CR1220 | |
U2 | SSD1_3V3_1 | 3.3V | Out | Pin 2, 4 | SSD PCIe connector | |
D36, D38, D40, C39 | - | |||||
FMCAF_1V8 | 1.8V | Out | Pin E39, G39, H40, F40 | - | ||
J21 | 12V_FMC_AF | 12.0V | Out | Pin C35, C37 | - | |
3V3VSBSSD1_3V3_2 | 3.3V | Out | Pin 70, 72, 74D32 | - | ||
FMCFSSD1_3V3_3 | 3.3V | Out | Pin 12D36, 14D38, 16D40, 18C39 | U3- | ||
DDRFMCAF_1V21V8 | 1.2V8V | Out | Pin 111E39, 112G39, 117, 118, 123, 124, 129, 130, 135, 136, 141, 142, 147, 148, 153, 154, 159, 160, 163 | DDR4 SO-DIMM socket | H40, F40 | - |
J4 | 12V | 12.0V | VPP_SPD | 2.5V | Out | Pin 255C35, 257, 259 |
Table 57: Power pin description of Peripherals' Connector
C37 | - | |||||||||
3V3VSB | 3.3V | Out | Pin D32 | - | ||||||
FMCB_3V3 | ||||||||||
XMOD / JTAG Designator | VCC / VCCIO Schematic Name | Voltage | Direction | Pins | Notes | |||||
---|---|---|---|---|---|---|---|---|---|---|
J24 | 3V3SB | 3.3V | Out | Pin | 5D36, D38, D40, C39 | - | ||||
FMCBC | Zynq MPSoC JTAGPS_1V8 | 1.8V | Out | Pin 6E39, G39, H40, F40 | - | |||||
J8 | 12V | 12.0V | J35 | 3V3SB | 3.3V | Out | Pin | 5C35, | 6C37 | SC CPLD JTAG |
Table 58: Power pin description of XMOD/JTAG Connector
...
PWR_IN_24V
...
24V
...
24V Power Jack
- | ||||
3V3VSB | 3.3V | Out | Pin D32 | - |
FMCC_3V3 | 3.3V | Out | Pin D36, D38, D40, C39 | - |
FMCBC_1V8 | 1.8V | Out | Pin E39, G39, H40, F40 | - |
J7 | 12V |
Table 59: Power pin description of main power supply connector
FMC Designator | VCC / VCCIO Schematic Name | Voltage | Direction | Pins | Notes | |
---|---|---|---|---|---|---|
J10 | 12V_FMC_AF12.0V | Out | Pin C35, C37 | - | ||
3V3VSB | 3.3V | Out | Pin D32 | - | ||
FMCAFMCD_3V3 | 3.3V | Out | Pin D36, D38, D40, C39 | - | ||
FMCAFFMCDE_1V8 | 1.8V | Out | Pin E39, G39, H40, F40 | - | ||
J21J6 | 12V_FMC_AF | 12.0V | Out | Pin C35, C37 | - | |
3V3VSB | 3.3V | Out | Pin D32 | - | ||
FMCFFMCE_3V3 | 3.3V | Out | Pin D36, D38, D40, C39 | - | ||
FMCAFFMCDE_1V8 | 1.8V | Out | Pin E39, G39, H40, F40 | - | J4 |
Table 60: Power pin description of FMC connectors
FAN Designator | VCC / VCCIO Schematic Name | Voltage | Direction | Pins | Notes | |
---|---|---|---|---|---|---|
J2 | - | 12.0V | Out | Pin 2 | headers for optional cooling FANs | |
J23 | - | 12.0V | Out | Pin 2 | ||
J33 | - | 12V12.0V | Out | Pin | C35, C37- | |
3V3VSB | 3.3V | Out | Pin D32 | - | ||
2 |
Table 61: Power pin description of FAN connectors
Bank Voltages
Bank | Schematic Name | Voltage | Voltage Range |
---|---|---|---|
500 (PS MIO) | PS_1V8 | 1.8V | all bank voltages fixed |
501 (PS MIO) | 3.3V |
3.3V | |
502 (PS MIO) | PS |
_1V8 | 1.8V |
503 (PS Config) | PS_1V8 | 1.8V |
504 (PS DDR) | DDR_1V2 | 1.2V |
64 HP | FMCDE_1V8 | 1.8V |
65 HP | FMCDE_1V8 | 1.8V |
66 HP | FMCDE_1V8 | 1.8V |
67 HP |
FMCBC_1V8 | 1.8V |
Table 60: Power pin description of FMC connectors
...
-
...
-
...
Table 61: Power pin description of FAN connectors
Bank Voltages
...
Bank
...
Voltage
...
Voltage Range
...
44 HD | FMCAF_1V8 | 1.8V |
47 HD | FMCBC_1V8 | 1.8V |
48 HD | FMCBC_1V8 | 1.8V |
49 HD | FMCBC_1V8 | 1.8V |
50 HD | FMCBC_1V8 | 1.8V |
Table 62: Zynq MPSoC PS/PL VCCO bank voltages
Variants Currently In Production
Trenz shop TEB9011 overview page | |
---|---|
English page | German page |
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Reference Document | Notes |
---|---|---|---|---|---|
VIN supply voltage | -0.3 | 28 | V | TEB0911 Schematic REV03 | - |
VBATT | -0.3 | 6 | V | TPS780180300 data sheet | 1.8V typical output |
PS GTR receiver input | -0.5 | 1.1 | V | Xilinx DS925 data sheet | - |
MGT reference clock input | -0.5 | 1.3 | V | Xilinx DS925 data sheet | supplied from FMC connectors |
GTH transcever input voltage | -0.5 | 1.2 | V | Xilinx DS925 data sheet | - |
PL I/O input voltage (HP / HD bank) | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet | PL bank VCCO voltages are fixed at 1.8V |
PS I/O input voltage | -0.5 | VCCO + 0.55 | V | Xilinx DS925 data sheet | see section 'bank voltages' for PS bank VCCO |
SC CPLD U27 I/O input voltage | -0.5 | 3.75 | V | Lattice MachXO2 familiy data sheet | - |
PLL clock generator input | -0.85 | 3.8 | V | Si5345/44/42 Rev D Data Sheet | supplied through SMA coax J25 |
Storage temperature | -20 | 60 | °C | TVS Diode Array 82402374 data sheet | - |
Table 63: Module absolute maximum ratings
Note |
---|
Assembly variants for higher storage temperature range are available on request. |
Recommended Operating Conditions
Parameter | Min | Max | Units | Reference Document | Notes |
---|---|---|---|---|---|
VIN supply voltage | 22 | 25 | V | Schematic REV03 | 24V nominal |
VBATT | 2.2 | 5.5 | V | TPS780180300 data sheet | supplied by 3.0V CR1220 battery |
PL I/O input voltage (HP / HD bank) | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet | PL bank VCCO voltages are fixed at 1.8V |
PS I/O input voltage | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet | see section 'bank voltages' for PS bank VCCO |
SC CPLD U27 I/O input voltage | -0.3 | 3.6 | V | Lattice MachXO2 familiy data sheet | - |
SC CPLD U27 differential I/O input voltage | 0 | 2.605 | V | Lattice MachXO2 familiy data sheet | - |
Operating temperature | 0 | 60 | °C | F455B / Xilinx DS925 data sheet | - |
Table 62: Zynq MPSoC PS/PL VCCO bank voltages
Variants Currently In Production
...
Technical Specifications
Absolute Maximum Ratings
...
Parameter
...
Units
...
Reference Document
...
VIN supply voltage
...
V
...
Storage temperature
...
°C
...
Table 63: Module absolute maximum ratings
Note |
---|
Assembly variants for higher storage temperature range are available on request. |
Recommended Operating Conditions
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | Operating temperature
Table 64: Module recommended operating conditions
...
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Extended grade: 0°C to +85°C.
Industrial grade: -40°C to +85°C.
Module operating temperature range depends also on customer design and cooling solution. Please contact us for optionsThe TEB0911 board operational temperature range is 0 °C ... 85 °C without FMC cooling fans M1 ... M6 and NGFF M.2 PCIe socket U2.
Physical Dimensions
Module Board size: ... mm 406mm × 234.30mm.. mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ... mm.
PCB thickness: 1... 65 mm.
Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.
...
Scroll Title | ||||
---|---|---|---|---|
| ||||
Scroll Title | ||||
---|---|---|---|---|
| ||||
Revision History
Hardware Revision History
Date | Revision | Notes | Link to PCN | Documentation Link |
---|---|---|---|---|
- | 03 | current Current available board revision | - | TEB0911-03 |
- | 02 | First Second production release | - | TEB0911-02 |
- | 01 | PrototypesFirst production release | - | TEB0911-01 |
Table 65: Module hardware revision history
Hardware revision number can be found on the PCB board together with the board model number separated by the dash.
...
HTML |
---|
<!-- Generate new entry: 1.add new row below first 2.Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number 3.Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> |
Date | Revision | Contributors | Description | ||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
|
|
| ||||||||||||||||||||||||||
2019-08-27 | v.184 | John Hartfiel |
| ||||||||||||||||||||||||||
2019-05-10 | v.183 | John Hartfiel |
| ||||||||||||||||||||||||||
2018-07-23 | v.182 | Ali Naseri |
| ||||||||||||||||||||||||||
-- | all |
|
Table 66: Document change history
...