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General Notes:
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Overview

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Wiki Link: Go to Base Folder of the Module or Carrier, for example : https://wiki.trenz-electronic.de/display/PD/TE0712
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Refer to https://wiki.trenz-electronic.de/display/PD/TEB0911+TRM for the current online version of this manual and other available documentation.

The Trenz Electronic TEB0911 UltraRack+ board is an industrial-grade motherboard integrating a Xilinx Zynq UltrascaleUltraScale+ MPSoC with 4 GByte Flash memory for configuration and operation, DDR4-SDRAM SODIMM SO-DIMM socket with 64-bit wide data bus, 24 22 MGT Lanes lanes and powerful switch-mode power supplies for all on-board voltages.. The motherboard TEB0911 board exposes the pins of the Zynq MPSoC 's pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq UltrascaleUltraScale+ MPSoC and for developing purposes. The motherboard board is capable to be fitted to a dedicated enclosure. On , whereby on the enclosure's rear and front panel, I/O's, LVDS-pairs and MGT interfaces lanes are accessible through 6 on-board FMC connectors and other standard high-speed interfaces for , namely USB3.0, SFP+, SSD, GbE, etc.

Key Features

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Refer to http://trenz.org/teb0911-info for the current online version of this manual and other available documentation.

Key Features

• Zynq UltraScale+ MPSoC
  • ZU6,ZU9 or ZU15 on 1156 Pin Package
• 64bit DDR4 SODIMM (PS connected)
• M2 PCIe SSD (1-Lane)
• eMMC (bootable)
• Dual QSPI Flash (bootable)
• System Controller(LCMXO2-7000HC)
  • Power Sequencing
  • IO Expander
• Configurable PLLs
• GTH/GTP Reference CLKs

Front Panel

• 4 x FMC
  • 4 GTH per FMC
  • 68 ZynqMP PL IO per FMC
• DisplayPort (2-Lanes)
• RJ34 ETH + Dual USB3 Combo
• Dual Stack SFP+
• SD (bootable)
• Status LEDs

Back Panel

• 2 x FMC
  • 4/2 GTH
  • 12 ZynqMP PL IO per FMC
  • 56 SC IO per FMC
• USB JTAG/UART ZynqMP
• USB JTAG/GPIO FMC
• CAN FD (DB9 Connector)
• SMA (external CLK)
• 5polig 24V power connector
• Single 24V main power supply
• Motherboard fitted to dedicated enclosure from Trenz ??
• 2x USB3.0 A Connector (Superspeed Host Port (Highspeed at USB2.0))
• Gigabit Ethernet RGMII PHY with RJ45 MegJack
• Dual SFP+ Connector (2x1 Cage)
• DDR4-SDRAM SODIMM socket (64bit bus width)
• SSD (Solid State Disk) Connector
• CAN FD Transceiver (10 Pin IDC connector and 6-pin header)
• 1x DisplayPort
• 4x On-board configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x  Microchip 24AA025E48T-I/OT)
• All carrier board peripherals' I²C interfaces muxed to MPSoC's I²C interface
• 6x FMC HPC Connectors
• 6x FMC Fans
• 3x Optional 4-wire PWM fan connectors
• 10 output programmable PLL clock generator Si5345A
• Quad programmable PLL clock generator SI5338A
• 1x SMA coaxial connectors for reference clock signal input
• MicroSD-Socket (bootable)
• 32 Gbit (4 GByte) on-board eMMC flash (8 banks a 4 Gbit)
• System Controller CPLD Lattice MachXO2 7000 HC
• 2x JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for programming MPSoC and SC CPLD
• On-board DC-DC PowerSoCs and LDOs

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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Main Components

Put top and bottom pics with labels of the real PCB here...

Table 1: TE0xxx-xx main components.

Add description list of PCB labels here...

Initial Delivery State

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Storage device name

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Content

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Notes

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Table 1: Initial delivery state of programmable devices on the module.

Boot Process

For the boot process prior to powering up the board settings must be done via DIP-Switch S3-3 and S3-4. Four boot modes can be selected:

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32-bit addressing, configured with dual on-board QSPI Flash Memory.

...

Table 2: Available boot modes of the on-board Zynq MPSoC

Refer also to the documentation of the SC CPLD firmware of the TEB0911 motherboard.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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FMC Connectors

The TEB0911 Ultrarack+ offers 6 FMC (FPGA Mezzanine Card) connectors which provides as an ANSI/VITA 57.1 standard a modular interface to the MPSoCs FPGA and exposes numerous of its I/O pins and MGT Lanes for use by other mezzanine modules and expansion cards.

The connector supports single ended and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.

Following diagram gives an overview of the FMC connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller CPLD U27:

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Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the FMC connectors  A - F:

FMC A Connector

...

J10

...

'FMCA_PG_C2M', 'FMCA_PG_M2C', 'FMCA_PRSNT'

Table 3: FMC A connector interfaces

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J10

(FMC A)

...

• B128_RX0_P
• B128_RX0_N
• B128_TX0_P
• B128_TX0_N

...

• J10-C6
• J10-C7
• J10-C2
• J10-C3

...

• MGTHRXP0_128, T33
• MGTHRXN0_128, T34
• MGTHTXP0_128, T29
• MGTHTXN0_128, T30

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• B128_RX1_P
• B128_RX1_N
• B128_TX1_P
• B128_TX1_N

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• J10-A2
• J10-A3
• J10-A22
• J10-A23

...

• MGTHRXP1_128, P33
• MGTHRXN1_128, P34
• MGTHTXP1_128, R31
• MGTHTXN1_128, R32

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• B128_RX2_P
• B128_RX2_N
• B128_TX2_P
• B128_TX2_N

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• J10-A6
• J10-A7
• J10-A26
• J10-A27

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• MGTHRXP2_128, N31
• MGTHRXN2_128, N32
• MGTHTXP2_128, P29
• MGTHTXN2_128, P30

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• B128_RX3_P
• B128_RX3_N
• B128_TX3_P
• B128_TX3_N

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• J10-A10
• J10-A11
• J10-A30
• J10-A31

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• MGTHRXP3_128, M33
• MGTHRXN3_128, M34
• MGTHTXP3_128, M29
• MGTHTXN3_128, M30

Main Components

1. SFP+ 2x1 cage with integrated LED light pipes, J9
2. DisplayPort connector, J12
3. USB3 A 2x , RJ45 1x (stacked), J13
4. FMC connector (FMC B), J4
5. FMC B cooling fan, M2
6. FMC connector (FMC C), J8
7. FMC C cooling fan, M3
8. FMC connector (FMC D), J7
9. FMC D cooling fan, M4
10. FMC connector (FMC E), J6
11. FMC E cooling fan, M5
12. I²C programming header of on-board PLL clock generator U17, J22
13. 4-Wire PWM fan connector, J23
14. Main Power Jack 24V, J1
15. CAN bus D-SUB 9-pin male connector, J3
16. CAN bus 6-pin header male, J15
17. XMOD JTAG header for access to System Controller CPLD, J35
    
18. XMOD JTAG header for access to Zynq MPSoC, J24
19. 4-Wire PWM fan connector, J33
20. Battery Holder CR1220, B1
21. SMA coaxial connector (PLL Si5345A U17 clock input), J25
22. Push Button, S1
23. Push Button, S2
24. DDR4 SO-DIMM socket, U3
25. 4-bit DIP-switch, S4
26. 4-bit DIP-switch, S3
27. FMC connector (FMC A), J10
28. FMC A cooling fan, M1
29. FMC connector (FMC F), J21
30. FMC F cooling fan, M6
31. NGFF M.2 PCIe socket (Key M), U2
32. SD Card socket, J11
33. User LEDs (3x green, 1x red) with LED light pipe, D13 ... D16
    
34. Green LEDs dedicated to USB3 hub U4, D17 ... D19
35. Red LED indicating FPGAs 'DONE' signal, D6
36. 4-Wire PWM fan connector, J2
37. Xilinx Zynq Ultrascale+ MPSoC, U1
    

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module

Boot Process

For the boot process prior to powering up the board settings must be done via DIP-Switch S3-3 and S3-4. Four boot modes can be selected:

Table 2: Available boot modes of the on-board Zynq MPSoC

Refer also to the documentation of the SC CPLD firmware of the TEB0911 board, section 'boot mode'.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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FMC Connectors

The TEB0911 Ultrarack+ offers 6 FMC (FPGA Mezzanine Card) connectors which provides as an ANSI/VITA 57.1 standard a modular interface to the MPSoCs FPGA and exposes numerous of its I/O pins and MGT lanes for use by other mezzanine modules and expansion cards.

The connector supports single ended and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.

Following diagram gives an overview of the FMC connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller CPLD U27:

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MGT lanes should be listed separately, as they are more specific than just general I/Os.
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Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the FMC connectors  A - F:

1. FMC A
2. FMC B
3. FMC C
4. FMC D
5. FMC E
6. FMC F
   

FMC A

FMC A Interfaces:

Table 4: FMC A connector MGT lanes

...

J10

(FMC A)

...

• B128_CLK0_P
• B128_CLK0_N

...

• J10-D4
• J10-D5

...

• MGTREFCLK0P_128, R27
• MGTREFCLK0N_128, R28

...

Table 5: FMC A connector clock signal input

Table 6: FMC A connector available VCC/VCCIO

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J10

(FMC A)

...

Enable by SC CPLD U27,

Signal: 'FAN_A_EN'

...

Table 3: FMC A connector interfaces

FMC A MGT Lanes:

Table 7: FMC A connector cooling fan

FMC F Connector

Table 4: FMC A connector MGT lanes

FMC A Clock Signals:

Table 5: FMC A connector clock signal input

FMC A VCC/VCCIO:

Table 6: FMC A connector available VCC/VCCIO

FMC A Cooling Fan:

Table 7: FMC A connector cooling fan

FMC F

FMC F Interfaces:

Table 8: FMC

...

J7
(FMC D)

...

2x Reference clock inputs to PL bank

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'FMCD_PG_C2M', 'FMCD_PG_M2C', 'FMCD_PRSNT'

...

J6
(FMC E)

...

2x Reference clock inputs to PL bank

...

'FMCE_PG_C2M', 'FMCE_PG_M2C', 'FMCE_PRSNT'

Table x: FMC connectors interfaces overview

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MGT lanes should be listed separately, as they are more specific than just general I/Os.
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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, FMC connector pin and FPGA pins:

Table x: MGT lanes

Below are listed MGT banks reference clock sources.

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Table x: MGT reference clock sources

TODO: FMC fans table, FMC available VCC/VCCIO table

XMOD Interface

JTAG access to the ... is provided through XMOD connector .... 

...

JTAG Signal

...

B2B Connector Pin

...

Table 5: JTAG interface signals.

Gigabit Ethernet Interface

USB3 Interface

SFP+ Interface

SSD Interface

DisplayPort Interface

DDR4 Memory Socket

CAN Interface

SD Card Interface

Describe SD Card interface  shortly here if the module has one...

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Table x: SD Card interface signals and connections.

PLL Clock Programing Interface

4-Wire PWM FAN Connectors

SMA Coax Clock Input

On-board Peripherals

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Components on the Module, like Flash, PLL, PHY...
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System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

The TEB0911 UltraRack is equipped with one System Controller CPLDs - Lattice Semiconductor LCMXO2-7000HC (MachXO2 Product Family) with the schematic designators U27.

The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic of the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

The Sytem Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO, PL IO-bank differential lanes and I²C interface.

The functionalities and configuration of the pins depend on the CPLDs' firmware. The documentations of the firmware of SC CPLD U27 contains detailed information on this matter.

Following block diagram visualizes the connection of the SC CPLDs with the Zynq Ultrascale+ MPSoC via PS (MIO), PL bank pins and I²C interface.

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Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

...

Table x: System Controller CPLD I/O pins.

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For the detailed function of the pins and signals, the internal signal assignment and implemented logic, look to the Wiki reference page SC CPLD of this module or into the bitstream file of the SC CPLD.
Add link to the Wiki reference page of the SC CPLD, if available.
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High-speed USB ULPI PHY

USB PHY (U9) is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U10).

...

Table 17: USB PHY interface connections

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

4-port USB3.0 Hub

On the carrier board there are up to 4 USB3.0 Super Speed ports available, which are also downward compatible to USB2.0 High Speed ports. The USB3.0 ports are provided by Cypress Semiconductor CYUSB3324 4-port USB3.0 Hub controller U4. The pin-strap configuration option of the USB3.0 Hub is disabled, so this controller gets the configuration data and parameter from the configuration EEPROM U5. The I²C interface of the EEPROM and the controller is also accessible by the Zynq Ultrascale+ MPSoC through I²C switch U16.

On the Upstream-side, this controller is connected to the MGT1 lane of MPSoC's PS GT bank to establish the USB3.0 data lane. For the USB2.0 interface, the controller is connected to the on-board USB2.0 PHY U9. The USB2.0 PHY is connected per ULPI interface (MIO pins 52..63) to MPSoC's MIO bank.

The USB3.0 Hub controller has also an ARM Cortex-M0 controller integrated, refer to the data sheet for further features and programmable options.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U12) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U13). The 125MHz PHY output clock (PHY_CLK125M) is routed to System Controller CPLD U17, pin 70.

...

Table 18: Ethernet PHY interface connections

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

8-Channel I²C Switches

All on-board and on-module peripherals with accessible I²C interface are muxed to the I²C interface of the Zynq Ultrascale+ MPSoC as master.

For this purpose, the TEB0911 carrier board is equipped with two 8-channel I²C switches provided by TCA9548A from Texas Instruments, together creating up to 16 switched I²C channels.

Refer to the data sheet of the TCA9548A chip how to address and and transmit data to the I²C slave devices through this switches.

The I²C bus works internally on-module with reference voltage 1.8V, it is connected to the MPSoC I²C interface via PS MIO bank (pins MIO38, MIO39) configured as master.

...

I²C addresses for on-board slave devices are listed in the table below:

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F connector interface

FMC F MGT Lanes:

Table 9: FMC F connector MGT lanes

FMC F Clock Signals:

Table 10: FMC F connector clock signal input

FMC F VCC/VCCIO:

Table 11: FMC F connector available VCC/VCCIO

FMC F Cooling Fan:

Table 12: FMC F connector cooling fan

FMC B

FMC B Interfaces:

Table 13: FMC B connector interfaces

FMC B MGT Lanes:

Table 14: FMC B connector MGT lanes

FMC B Clock Signals:

Table 15: FMC B connector clock signal input

FMC B VCC/VCCIO:

Table 16: FMC B connector available VCC/VCCIO

FMC B Cooling Fan:

Table 17: FMC B connector cooling fan

FMC C

FMC C Interfaces:

Table 18: FMC C connector interfaces

FMC C MGT Lanes:

Table 19: FMC C connector MGT lanes

FMC C Clock Signals:

Table 20: FMC C connector clock signal input

FMC C VCC/VCCIO:

Table 21: FMC C connector available VCC/VCCIO

FMC C Cooling Fan:

Table 22: FMC C connector cooling fan

FMC D

FMC D Interfaces:

Table 23: FMC D connector interfaces

FMC D MGT Lanes:

Table 24: FMC D connector MGT lanes

FMC D Clock Signals:

Table 25: FMC D connector clock signal input

FMC D VCC/VCCIO:

Table 26: FMC D connector available VCC/VCCIO

FMC D Cooling Fan:

Table 27: FMC D connector cooling fan

FMC E

FMC E Interfaces:

Table 28: FMC E connector interfaces

FMC E MGT Lanes:

Table 29: FMC E connector MGT lanes

FMC E Clock Signals:

Table 30: FMC E connector clock signal input

FMC E VCC/VCCIO:

Table 31: FMC E connector available VCC/VCCIO

FMC E Cooling Fan:

Table 32: FMC E connector cooling fan

XMOD JTAG Interface

JTAG access to the Zynq MPSoC and SC CPLD is provided through XMOD header J24 and J35:

Signal Assignment of XMOD header J24 and J35

Table 33: XMOD interface signals

The JTAG interfaces of the TEB0911 UltraRack board can accessed with the XMOD-FT2232H adapter-board TE0790. The on-board devices Zynq MPSoC U1 and SC CPLD U27 can be programmed via USB2.0 interface of the TE0790 programmer.

XMOD-Header J24 is designated to program the Zynq Ultrascale+ MPSoC via USB interface, the 4 GPIO/UART pins (XMOD2_A/B/E/G) of this header are routed to the System Controller CPLD U27.

XMOD-Header J35 is designated to program the System Controller CPLD U27 via USB interface, the 4 GPIO/UART pins (XMOD1_A/B/E/G) of this header are also routed to the System Controller CPLD U27.
To program the System Controller CPLD, the JTAG interface of this devices have to be activated by DIP-switch S3-2.  J35 JTAG is used for FMC JTAG, is JTAGENB is low (see CPLD Firmware).

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO on both headers J24 and J35 will be sourced by the on-board supply voltages. Set the XMOD DIP-switch with the setting:

Table 34: XMOD adapter board DIP-switch positions for voltage configuration

Gigabit Ethernet Interface

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC U20. The Ethernet PHY RGMII interface is connected to the Zynq MPSoC Ethernet interface of the PS MIO bank 502. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The LEDs of the RJ-45 MegJack J13 are connected to the System Controller CPLD bank 2, pins Y12, Y13 and Y14.

Following table describes the signals and control lines of the Gigabit Ethernet interface of the board:

Table 35: Ethernet PHY interface connections

USB3 Interface

On the TEB0911 board two USB3 Superspeed ports are available to the user, which are downward compatible to USB2 Highspeed.

The 4-port USB3 hub is connected to the Zynq MPSoC's PS GTR bank, the USB2 PHY is connected to the PS MIO bank 502:

Table 36: USB3 signals and interfaces

SFP+ Interface

The TEB0911 board provides the high speed MGT interface connectors "SFP+" (Enhanced small form-factor pluggable) with data transmission rates up to 10 Gbit/s.

Block diagram below shows the dependencies between the implied devices which establish the SFP+ interface:

Table 37: SFP+ signals and interfaces

SSD Interface

On the TEB0911 UltraRack board one SSD interface is available provided by a NGFF (Next Generation Form Faktor) M.2 socket (Key M) which supports data transmission rates for PCIe3, SATA3 and USB3 interfaces.

Table 38: SSD signals and interfaces

DisplayPort Interface

The TEB0911 board provides the high speed DisplayPort interface for visual output. The DisplayPort is connected with two transmit LVDS-pairs of bank 505 PS GTR lanes. Additionally the auxiliary transmit line is established by the SC CPLD in conjunction with a LVDS Line Driver/Receiver.

Follwowing table contains a brief description of the MGT lanes and control and status signals of the DisplayPort interface:

Table 39: DisplayPort signals and interfaces