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Table of Contents

Table of Contents

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  1. Xilinx Artix-7 FPGA (XC7A series), U4
  2. 16 MByte SPI Flash, U7
  3. B2B connector Samtec Razor Beam™ LSHM-150, JM2
  4. B2B connector Samtec Razor Beam™ LSHM-150, JM1
  5. 25 MHz oscillator, U8
  6. Single output low-dropout linear regulator (1.2V_MGT), U6
  7. Single output low-dropout linear regulator (1.0V_MGT), U5
  8. Low-jitter precision LVDS 125 MHz oscillator (GT Clock), U2
  9. Red indication LED, D4
  10. Step-down DC-DC converter (1.0V), U1
  11. PFET load switch with configurable slew rate (3.3V), Q1
  12. Low-power step-down DC-DC converter (1.8V), U3
  13. Voltage detector for circuit initialization and timing supervision, U23 

 


Initial Delivery State

Storage device name

Content

Notes

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor

SPI Flash Quad Enable bit

Programmed

 

SPI Flash main array

demo design

 


eFUSE USER

Not programmed

 

eFUSE Security

Not programmed

 
 



Signals, Interfaces and Pins

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FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
14JM16VCCIO_0 
14JM236VCCIO_0NB! 17 LVDS pairs possible.
15JM248VCCIO15Supplied by the baseboard.
34JM148VCCIO34Supplied by the baseboard.
216JM116

MGT_AVCC

MGT_AVTT

4 x GTP lanes.

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LED

Color

FPGA

Notes

D4

Red

K18 


Page break

Clocking

Clock

Default Frequency

IC

FPGA

Notes

CLK25MHz

25 MHz

U8

T14

Frequency depends on the module variant. Output is compatible to 3.3V and 1.8V I/O standard of the FPGA bank.
MGT_CLK

125MHz

U2

B6/B5

Frequency depends on the module variant

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Test Condition (25 °C ambient)VIN Current mANotes
TE0714-35, TEBT0714, empty design, GT not enabled110mA 

Actual power consumption depends on the FPGA design and ambient temperature.

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DateRevision

Notes

PCN LinkDocumentation Link
2016-08-0402VCCIO0 added to B2BPCN-20160815TE0714-02

01

-

-TE0714-01

Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

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