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General Notes:
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Refer to https://wiki.trenz-electronic.de/display/PD/<name>TEB0911+TRM for the current online version of this manual and other available documentation.

The Trenz Electronic TEB0911 UltraRack+ board is an industrial-grade motherboard integrating a Xilinx Zynq Ultrascale+ MPSoC with 4 GByte Flash memory for configuration and operation, DDR4-SDRAM SODIMM -Socket socket with 64-bit wide data bus, 20 Gigabit transceivers and powerful switch-mode power supplies for all on-board voltages.. The motherboard exposes the Zynq MPSoC's pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq Ultrascale+ MPSoC and for developing purposes. The motherboard is capable to be fitted to a dedicated enclosure. On the enclosure's rear and front panel, I/O's and MGT interfaces are accessible through 6 on-board FMC connectors and other standard high-speed interfaces for USB3.0, SFP+, SSD, GbE, etc.

Key Features

• Single 24V main power supply
• Motherboard fitted to a dedicated enclosure
• On-board Power- / Reset-Switches
• 3x Optional 4-wire PWM fan connectors
• from Trenz ??
• 2x USB3.0 A Connector (Superspeed Host Port (Highspeed at USB2.0))
• Gigabit Ethernet RGMII PHY with RJ45 MegJack
• Dual SFP+ Connector (2x1 Cage)
• DDR4-SDRAM SODIMM socket (64bit bus width)
• SSD (Solid State Disk) ConnectorSSD Slot
• CAN FD Transceiver (10 Pin IDC connector and 6-pin header)
• 1x DisplayPort
• 4x On-board configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x  Microchip 24AA025E48T-I/OT)
• Dual SFP+ Connector (2x1 Cage)
• 1x DisplayPort (single lane)
• 1x SSD Connector
• 2x USB3.0 A Connector (Superspeed Host Port (Highspeed at USB2.0))
• 6x FMC HPC Connectors
• 6x FMC Fans
• Gigabit Ethernet RGMII PHY with RJ45 MegJack
• All carrier board peripherals' I²C interfaces muxed to MPSoC's I²C interface
• 6x FMC HPC Connectors
• 6x FMC Fans
• 3x Optional 4-wire PWM fan connectors
• 10 output programmable PLL clock generator Si5345AAll carrier board peripherals' I²C interfaces muxed to MPSoC's I²C interface
• Quad programmable PLL clock generator SI5338A
• 1x SMA coaxial connectors for reference clock signal input
• MicroSD-Socket (bootable)
• 32 Gbit (4 GByte) on-board eMMC flash (8 banks a 4 Gbit)
• System Controller CPLD Lattice MachXO2 7000 HHC
• 2x JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for programming MPSoC and SC CPLD
• On-board DC-DC PowerSoCs and LDOs

Additional assembly options are available for cost or performance optimization upon request.

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Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector JM..

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MODE Signal State

...

High or open

...

SD Card

...

Low or ground

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QSPI Interface

For the boot process prior to powering up the board settings must be done via DIP-Switch S3-3 and S3-4. Four boot modes can be selected:

Table 2: Available boot modes of the on-board Zynq MPSoC

Refer also to the documentation of the SC CPLD firmware of the TEB0911 motherboardTable 2: Selecting power-on boot device.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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FMC HPC Connectors

I/O signals connected to the SoCs I/O bank and B2B connector: 

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Table x: General overview of PL I/O signals connected to the B2B connectors.

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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Table x: MGT lanes.

Below are listed MGT banks reference clock sources.

Table x: MGT reference clock sources.

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JTAG access to the ... is provided through B2B connector .... 

Table 5: JTAG interface signals.

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Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Table x: System Controller CPLD I/O pins.

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Note that table column says "Signal Name", it should match the name used on the schematic.

Table x: Quad SPI interface signals and connections.

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Describe SD Card interface  shortly here if the module has one...

Table x: SD Card interface signals and connections.

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On board Gigabit Ethernet PHY is provided with ...

Ethernet PHY connection

Table x: ...

USB Interface

USB PHY is provided with ...

Table x: ...

The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

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On-board I²C devices are connected to MIO.. and MIO.. which are configured as I²C... by default. I²C addresses for on-board devices are listed in the table below:

Table x: I²C slave device addresses.

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There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

 Table : Programmable quad PLL clock generator inputs and outputs.

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The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Table : Reference clock signals.

On-board LEDs

Table : On-board LEDs.

Power and Power-On Sequence

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Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table : Typical power consumption.

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NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.

Table : Module power rails.

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Bank Voltages

Table : Module PL I/O bank voltages.

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NB! Note that here we look at the module as a whole, so you just can't rely only on junction temperature or max voltage of particular SoC or FPGA chip on the module. See examples in the table below.

Table : Module variants.

Technical Specifications

Absolute Maximum Ratings

Table : Module absolute maximum ratings.

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Recommended Operating Conditions

Table : Module recommended operating conditions.

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Hardware Revision History

Table : Module hardware revision history.

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v.58

Table : Document change history.

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