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Table of Contents
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Overview
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Refer to https://wiki.trenz-electronic.de/display/PD/TEB0911+TRM for the current online version of this manual and other available documentation. |
The Trenz Electronic TEB0911 UltraRack+ board is an industrial-grade motherboard integrating a Xilinx Zynq Ultrascale+ MPSoC with 4 GByte Flash memory for configuration and operation, DDR4-SDRAM SODIMM socket with 64-bit wide data bus, 24 MGT Lanes and powerful switch-mode power supplies for all on-board voltages.. The motherboard exposes the Zynq MPSoC's pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq Ultrascale+ MPSoC and for developing purposes. The motherboard is capable to be fitted to a dedicated enclosure. On the enclosure's rear and front panel, I/O's and MGT interfaces are accessible through 6 on-board FMC connectors and other standard high-speed interfaces for USB3.0, SFP+, SSD, GbE, etc.
Key Features
- Single 24V main power supply
- 2x USB3 A Connector (Superspeed Host Port (Highspeed at USB2))
- Gigabit Ethernet RGMII PHY with RJ45 MegJack
- Dual SFP+ Connector (2x1 Cage)
- DDR4-SDRAM SODIMM socket (64bit bus width)
- SSD (Solid State Disk) Connector
- CAN FD Transceiver (10 Pin IDC connector and 6-pin header)
- 1x DisplayPort
- 4x On-board configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT)
- All carrier board peripherals' I²C interfaces muxed to MPSoC's I²C interface
- 6x FMC HPC Connectors
- 6x FMC Fans
- 3x Optional 4-wire PWM fan connectors
- 10 output programmable PLL clock generator Si5345A
- Quad programmable PLL clock generator SI5338A
- 1x SMA coaxial connectors for reference clock signal input
- MicroSD-Socket (bootable)
- 32 Gbit (4 GByte) on-board eMMC flash (8 banks a 4 Gbit)
- System Controller CPLD Lattice MachXO2 7000 HC
- 2x JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for programming MPSoC and SC CPLD
- On-board DC-DC PowerSoCs and LDOs
Additional assembly options are available for cost or performance optimization upon request.
Block Diagram
Put your block diagram here...
Figure 1: TE0xxx-xx block diagram.
Main Components
Put top and bottom pics with labels of the real PCB here...
Table 1: TE0xxx-xx main components.
Add description list of PCB labels here...
Initial Delivery State
...
Storage device name
...
Content
...
Notes
...
Table 1: Initial delivery state of programmable devices on the module.
Boot Process
For the boot process prior to powering up the board settings must be done via DIP-Switch S3-3 and S3-4. Four boot modes can be selected:
...
32-bit addressing, configured with dual on-board QSPI Flash Memory.
...
Table 2: Available boot modes of the on-board Zynq MPSoC
Refer also to the documentation of the SC CPLD firmware of the TEB0911 motherboard.
Signals, Interfaces and Pins
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Connections and Interfaces or B2B Pin's which are accessible by User
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FMC Connectors
The TEB0911 Ultrarack+ offers 6 FMC (FPGA Mezzanine Card) connectors which provides as an ANSI/VITA 57.1 standard a modular interface to the MPSoCs FPGA and exposes numerous of its I/O pins and MGT Lanes for use by other mezzanine modules and expansion cards.
The connector supports single ended and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.
Following diagram gives an overview of the FMC connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller CPLD U27:
| draw.io Diagram | ||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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Figure x: General overview of the FMC connectors
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MGT lanes should be listed separately, as they are more specific than just general I/Os.
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Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the FMC connectors A - F:
...
FMC A
FMC A Interfaces:
...
J10
...
'FMCA_PG_C2M', 'FMCA_PG_M2C', 'FMCA_PRSNT'
...
FMC A MGT Lanes:
...
J10
(FMC A)
...
- B128_RX0_P
- B128_RX0_N
- B128_TX0_P
- B128_TX0_N
...
- J10-C6
- J10-C7
- J10-C2
- J10-C3
...
- MGTHRXP0_128, T33
- MGTHRXN0_128, T34
- MGTHTXP0_128, T29
- MGTHTXN0_128, T30
...
- B128_RX1_P
- B128_RX1_N
- B128_TX1_P
- B128_TX1_N
...
- J10-A2
- J10-A3
- J10-A22
- J10-A23
...
- MGTHRXP1_128, P33
- MGTHRXN1_128, P34
- MGTHTXP1_128, R31
- MGTHTXN1_128, R32
...
- B128_RX2_P
- B128_RX2_N
- B128_TX2_P
- B128_TX2_N
...
- J10-A6
- J10-A7
- J10-A26
- J10-A27
...
- MGTHRXP2_128, N31
- MGTHRXN2_128, N32
- MGTHTXP2_128, P29
- MGTHTXN2_128, P30
...
- B128_RX3_P
- B128_RX3_N
- B128_TX3_P
- B128_TX3_N
...
- J10-A10
- J10-A11
- J10-A30
- J10-A31
...
- MGTHRXP3_128, M33
- MGTHRXN3_128, M34
- MGTHTXP3_128, M29
- MGTHTXN3_128, M30
...
FMC A Clock Signals:
...
J10
(FMC A)
...
- B128_CLK0_P
- B128_CLK0_N
...
- J10-D4
- J10-D5
...
- MGTREFCLK0P_128, R27
- MGTREFCLK0N_128, R28
...
FMC A VCC/VCCIO:
...
J10
(FMC A)
...
- J10-D36
- J10-D38
- J10-D40
- J10-C39
...
DCDC U32,
max. cur.: 5A
...
Enable by SC CPLD U27, bank 2, pin Y18
Signal: 'EN_A_3V3'
...
- J10-D32
...
DCDC U50,
...
- J10-C35
- J10-C37
...
DCDC U51,
max. cur.: 5A
...
- J10-H40
- J10-G39
- J10-F40
- J10-E39
...
DCDC U39,
max. cur.: 5A
...
Enable by SC CPLD U27, bank 2, pin W19
Signal: 'EN_AF_1V8'
...
FMC A Cooling Fan:
...
J10
(FMC A)
...
Enable by SC CPLD U27, bank 2, pin Y19
Signal: 'FAN_A_EN'
...
Table 7: FMC A connector cooling fan
...
FMC F
FMC F Interfaces:
...
J21
...
'FMCF_PG_C2M', 'FMCF_PG_M2C', 'FMCF_PRSNT'
...
FMC F MGT Lanes:
...
J21
(FMC F)
...
- B129_RX0_P
- B129_RX0_N
- B129_TX0_P
- B129_TX0_N
...
- J21-C6
- J21-C7
- J21-C2
- J21-C3
...
- MGTHRXP0_129, L31
- MGTHRXN0_129, L32
- MGTHTXP0_129, K29
- MGTHTXN0_129, K30
...
- B129_RX1_P
- B129_RX1_N
- B129_TX1_P
- B129_TX1_N
...
- J21-A2
- J21-A3
- J21-A22
- J21-A23
...
- MGTHRXP1_129, K33
- MGTHRXN1_129, K34
- MGTHTXP1_129, J31
- MGTHTXN1_129, J32
...
FMC F Clock Signals:
...
J21
(FMC F)
...
- B129_CLK0_P
- B129_CLK0_N
...
- J21-D4
- J21-D5
...
- MGTREFCLK0P_129, L27
- MGTREFCLK0N_129, L28
...
FMC F VCC/VCCIO:
...
J21
(FMC F)
...
- J21-D36
- J21-D38
- J21-D40
- J21-C39
...
DCDC U42,
max. cur.: 5A
...
Enable by SC CPLD U27, bank 2, pin Y10
Signal: 'EN_F_3V3'
...
- J21-D32
...
DCDC U50,
...
- J21-C35
- J21-C37
...
DCDC U51,
max. cur.: 5A
...
- J21-H40
- J21-G39
- J21-F40
- J21-E39
...
DCDC U39,
max. cur.: 5A
...
Enable by SC CPLD U27, bank 2, pin W19
Signal: 'EN_AF_1V8'
...
FMC F Cooling Fan:
...
J21
(FMC F)
...
Enable by SC CPLD U27, bank 2, pin W18
Signal: 'FAN_F_EN'
...
Table 12: FMC F connector cooling fan
...
FMC B
FMC B Interfaces:
...
J4
(FMC B)
...
2x Reference clock inputs to PL bank
...
'FMCB_PG_C2M', 'FMCB_PG_M2C', 'FMCB_PRSNT'
...
FMC B MGT Lanes:
...
J4
(FMC B)
...
- B130_RX3_P
- B130_RX3_N
- B130_TX3_P
- B130_TX3_N
...
- J4-C6
- J4-C7
- J4-C2
- J4-C3
...
- MGTHRXP3_130, B33
- MGTHRXN3_130, B34
- MGTHTXP3_130, A31
- MGTHTXN3_130, A32
...
- B130_RX2_P
- B130_RX2_N
- B130_TX2_P
- B130_TX2_N
...
- J4-A2
- J4-A3
- J4-A22
- J4-A23
...
- MGTHRXP2_130, C31
- MGTHRXN2_130, C32
- MGTHTXP2_130, B29
- MGTHTXN2_130, B30
...
- B130_RX1_P
- B130_RX1_N
- B130_TX1_P
- B130_TX1_N
...
- J4-A6
- J4-A7
- J4-A26
- J4-A27
...
- MGTHRXP1_130, D33
- MGTHRXN1_130, D34
- MGTHTXP1_130, D29
- MGTHTXN1_130, D30
...
- B130_RX0_P
- B130_RX0_N
- B130_TX0_P
- B130_TX0_N
...
- J4-A10
- J4-A11
- J4-A30
- J4-A31
...
- MGTHRXP0_130, E31
- MGTHRXN0_130, E32
- MGTHTXP0_130, F29
- MGTHTXN0_130, F30
...
FMC B Clock Signals:
...
J4
(FMC B)
...
- B130_CLK0_P
- B130_CLK0_N
...
- J4-D4
- J4-D5
...
- MGTREFCLK0P_130, G27
- MGTREFCLK0N_130, G28
...
- B_CLK0_M2C_P
- B_CLK0_M2C_N
...
- J4-H4
- J4-H5
...
- IO_L6P_HDGC_48, F17
- IO_L6N_HDGC_48, F18
...
- B_CLK1_M2C_P
- B_CLK1_M2C_N
...
- J4-G2
- J4-G3
...
- IO_L5P_HDGC_48, G18
- IO_L5N_HDGC_48, G19
...
FMC B VCC/VCCIO:
...
J4
(FMC B)
...
- J4-D36
- J4-D38
- J4-D40
- J4-C39
...
DCDC U33,
max. cur.: 5A
...
Enable by SC CPLD U27, bank 0, pin G11
Signal: 'EN_B_3V3'
...
- J4-D32
...
DCDC U50,
...
- J4-C35
- J4-C37
...
DCDC U82,
max. cur.: 8A
...
not dedicated for FMC connectors
...
- J4-H40
- J4-G39
- J4-F40
- J4-E39
...
DCDC U40,
max. cur.: 5A
...
Enable by SC CPLD U27, bank 0, pin A3
Signal: 'EN_BC_1V8'
...
FMC B Cooling Fan:
...
J4
(FMC B)
...
Enable by SC CPLD U27, bank 0, pin A2
Signal: 'FAN_B_EN'
...
Table 17: FMC B connector cooling fan
...
FMC C
FMC C Interfaces:
...
J8
(FMC C)
...
2x Reference clock inputs to PL bank
...
'FMCC_PG_C2M', 'FMCC_PG_M2C', 'FMCC_PRSNT'
...
FMC C MGT Lanes:
...
J8
(FMC C)
...
- B230_RX3_P
- B230_RX3_N
- B230_TX3_P
- B230_TX3_N
...
- J8-C6
- J8-C7
- J8-C2
- J8-C3
...
- MGTHRXP3_230, A4
- MGTHRXN3_230, A3
- MGTHTXP3_230, A8
- MGTHTXN3_230, A7
...
- B230_RX2_P
- B230_RX2_N
- B230_TX2_P
- B230_TX2_N
...
- J8-A2
- J8-A3
- J8-A22
- J8-A23
...
- MGTHRXP2_230, B2
- MGTHRXN2_230, B1
- MGTHTXP2_230, B6
- MGTHTXN2_230, B5
...
- B230_RX1_P
- B230_RX1_N
- B230_TX1_P
- B230_TX1_N
...
- J8-A6
- J8-A7
- J8-A26
- J8-A27
...
- MGTHRXP1_230, C4
- MGTHRXN1_230, C3
- MGTHTXP1_230, D6
- MGTHTXN1_230, D5
...
- B230_RX0_P
- B230_RX0_N
- B230_TX0_P
- B230_TX0_N
...
- J8-A10
- J8-A11
- J8-A30
- J8-A31
...
- MGTHRXP0_230, D2
- MGTHRXN0_230, D1
- MGTHTXP0_230, E4
- MGTHTXN0_230, E3
...
FMC C Clock Signals:
...
J8
(FMC C)
...
- B230_CLK0_P
- B230_CLK0_N
...
- J8-D4
- J8-D5
...
- MGTREFCLK0P_230, C8
- MGTREFCLK0N_230, C7
...
- C_CLK0_M2C_P
- C_CLK0_M2C_N
...
- J8-H4
- J8-H5
...
- IO_L7P_HDGC_50, J12
- IO_L7N_HDGC_50, H12
...
- C_CLK1_M2C_P
- C_CLK1_M2C_N
...
- J8-G2
- J8-G3
...
- IO_L8P_HDGC_50, H13
- IO_L8N_HDGC_50, G13
...
FMC C VCC/VCCIO:
...
J8
(FMC C)
...
- J8-D36
- J8-D38
- J8-D40
- J8-C39
...
DCDC U34,
max. cur.: 5A
...
Enable by SC CPLD U27, bank 0, pin E11
Signal: 'EN_C_3V3'
...
- J8-D32
...
DCDC U50,
...
- J8-C35
- J8-C37
...
DCDC U82,
max. cur.: 8A
...
not dedicated for FMC connectors
...
- J8-H40
- J8-G39
- J8-F40
- J8-E39
...
DCDC U40,
max. cur.: 5A
...
Enable by SC CPLD U27, bank 0, pin A3
Signal: 'EN_BC_1V8'
...
FMC C Cooling Fan:
...
J8
(FMC C)
...
Enable by SC CPLD U27, bank 0, pin B3
Signal: 'FAN_C_EN'
...
Table 22: FMC C connector cooling fan
...
FMC D
FMC D Interfaces:
...
J7
(FMC D)
...
2x Reference clock inputs to PL bank
...
'FMCD_PG_C2M', 'FMCD_PG_M2C', 'FMCD_PRSNT'
...
FMC D MGT Lanes:
...
J7
(FMC D)
...
- B229_RX3_P
- B229_RX3_N
- B229_TX3_P
- B229_TX3_N
...
- J7-C6
- J7-C7
- J7-C2
- J7-C3
...
- MGTHRXP3_229, F2
- MGTHRXN3_229, F1
- MGTHTXP3_229, F6
- MGTHTXN3_229, F5
...
- B229_RX2_P
- B229_RX2_N
- B229_TX2_P
- B229_TX2_N
...
- J7-A2
- J7-A3
- J7-A22
- J7-A23
...
- MGTHRXP2_229, H2
- MGTHRXN2_229, H1
- MGTHTXP2_229, G4
- MGTHTXN2_229, G3
...
- B229_RX1_P
- B229_RX1_N
- B229_TX1_P
- B229_TX1_N
...
- J7-A6
- J7-A7
- J7-A26
- J7-A27
...
- MGTHRXP1_229, J4
- MGTHRXN1_229, J3
- MGTHTXP1_229, H6
- MGTHTXN1_229, H5
...
- B229_RX0_P
- B229_RX0_N
- B229_TX0_P
- B229_TX0_N
...
- J7-A10
- J7-A11
- J7-A30
- J7-A31
...
- MGTHRXP0_229, K2
- MGTHRXN0_229, K1
- MGTHTXP0_229, K6
- MGTHTXN0_229, K5
...
FMC D Clock Signals:
...
J7
(FMC D)
...
- B229_CLK0_P
- B229_CLK0_N
...
- J7-D4
- J7-D5
...
- MGTREFCLK0P_229, G8
- MGTREFCLK0N_229, G7
...
- D_CLK0_M2C_P
- D_CLK0_M2C_N
...
- J7-H4
- J7-H5
...
- IO_L14P_T2L_N2_GC_65, AG5
- IO_L14N_T2L_N3_GC_65, AG4
...
- D_CLK1_M2C_P
- D_CLK1_M2C_N
...
- J7-G2
- J7-G3
...
- IO_L13P_T2L_N0_GC_QBC_65, AE5
- IO_L13N_T2L_N1_GC_QBC_65, AF5
...
FMC D VCC/VCCIO:
...
J7
(FMC D)
...
- J7-D36
- J7-D38
- J7-D40
- J7-C39
...
DCDC U35,
max. cur.: 5A
...
Enable by SC CPLD U27, bank 0, pin F8
Signal: 'EN_D_3V3'
...
- J7-D32
...
DCDC U50,
...
- J7-C35
- J7-C37
...
DCDC U82,
max. cur.: 8A
...
not dedicated for FMC connectors
...
- J7-H40
- J7-G39
- J7-F40
- J7-E39
...
DCDC U41,
max. cur.: 5A
...
Enable by SC CPLD U27, bank 0, pin C5
Signal: 'EN_DE_1V8'
...
FMC D Cooling Fan:
...
J7
(FMC D)
...
Enable by SC CPLD U27, bank 0, pin D7
Signal: 'FAN_D_EN'
...
Table 27: FMC D connector cooling fan
...
FMC E
FMC E Interfaces:
...
J6
(FMC E)
...
2x Reference clock inputs to PL bank
...
'FMCE_PG_C2M', 'FMCE_PG_M2C', 'FMCE_PRSNT'
...
FMC E MGT Lanes:
...
J6
(FMC E)
...
- B228_RX3_P
- B228_RX3_N
- B228_TX3_P
- B228_TX3_N
...
- J6-C6
- J6-C7
- J6-C2
- J6-C3
...
- MGTHRXP3_228, L4
- MGTHRXN3_228, L3
- MGTHTXP3_228, M6
- MGTHTXN3_228, M5
...
- B228_RX2_P
- B228_RX2_N
- B228_TX2_P
- B228_TX2_N
...
- J6-A2
- J6-A3
- J6-A22
- J6-A23
...
- MGTHRXP2_228, M2
- MGTHRXN2_228, M1
- MGTHTXP2_228, N4
- MGTHTXN2_228, N3
...
- B228_RX1_P
- B228_RX1_N
- B228_TX1_P
- B228_TX1_N
...
- J6-A6
- J6-A7
- J6-A26
- J6-A27
...
- MGTHRXP1_228, P2
- MGTHRXN1_228, P1
- MGTHTXP1_228, P6
- MGTHTXN1_228, P5
...
- B228_RX0_P
- B228_RX0_N
- B228_TX0_P
- B228_TX0_N
...
- J6-A10
- J6-A11
- J6-A30
- J6-A31
...
- MGTHRXP0_228, T2
- MGTHRXN0_228, T1
- MGTHTXP0_228, R4
- MGTHTXN0_228, R3
...
FMC E Clock Signals:
...
J6
(FMC E)
...
- B228_CLK0_P
- B228_CLK0_N
...
- J6-D4
- J6-D5
...
- MGTREFCLK0P_228, L8
- MGTREFCLK0N_228, L7
...
- E_CLK0_M2C_P
- E_CLK0_M2C_N
...
- J6-H4
- J6-H5
...
- IO_L12P_T1U_N10_GC_64, AL8
- IO_L12N_T1U_N11_GC_64, AL7
...
- E_CLK1_M2C_P
- E_CLK1_M2C_N
...
- J6-G2
- J6-G3
...
- IO_L11P_T1U_N8_GC_64, AK8
- IO_L11N_T1U_N9_GC_64, AK7
...
FMC E VCC/VCCIO:
...
J6
(FMC E)
...
- J6-D36
- J6-D38
- J6-D40
- J6-C39
...
DCDC U36,
max. cur.: 5A
...
Enable by SC CPLD U27, bank 0, pin E8
Signal: 'EN_E_3V3'
...
- J6-D32
...
DCDC U50,
...
- J6-C35
- J6-C37
...
DCDC U82,
max. cur.: 8A
...
not dedicated for FMC connectors
...
- J6-H40
- J6-G39
- J6-F40
- J6-E39
...
DCDC U41,
max. cur.: 5A
...
Enable by SC CPLD U27, bank 0, pin C5
Signal: 'EN_DE_1V8'
...
FMC E Cooling Fan:
...
J6
(FMC E)
...
Enable by SC CPLD U27, bank 0, pin D6
Signal: 'FAN_E_EN'
...
Table 32: FMC E connector cooling fan
XMOD JTAG Interface
JTAG access to the Zynq MPSoC and SC CPLD is provided through XMOD header J24 and J35.
| draw.io Diagram | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
...
Signal Assignment of XMOD header J24 and J35
...
Signal Schematic Name
...
XMOD Header
J24
...
GPIO/
UART
...
XMOD Header
J35
...
GPIO/
UART
...
The JTAG interfaces of the TEB0911 UltraRack board can accessed with the XMOD-FT2232H adapter-board TE0790. The on-board devices Zynq MPSoC U1 and SC CPLD U27 can be programmed via USB2.0 interface of the TE0790 board.
XMOD-Header J24 is designated to program the Zynq Ultrascale+ MPSoC via USB interface, the 4 GPIO/UART pins (XMOD2_A/B/E/G) of this header are routed to the System Controller CPLD U27.
XMOD-Header J35 is designated to program the System Controller CPLD U27 via USB interface, the 4 GPIO/UART pins (XMOD1_A/B/E/G) of this header are also routed to the System Controller CPLD U27.
To program the System Controller CPLD, the JTAG interface of this devices have to be activated by DIP-switch S3-2.
When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO on both headers J24 and J35 will be sourced by the on-board supply voltages. Set the XMOD DIP-switch with the setting:
...
Table 34: XMOD adapter board DIP-switch positions for voltage configuration
| Note |
|---|
Use Xilinx compatible TE0790 adapter board (designation TE-0790-xx with out 'L') to program the Xilinx Zynq devices. The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download. |
Gigabit Ethernet Interface
On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC U20. The Ethernet PHY RGMII interface is connected to the Zynq MPSoC Ethernet interface of the PS MIO bank 502. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The LEDs of the RJ-45 MegJack J13 are connected to the System Controller CPLD bank 2, pins Y12, Y13 and Y14.
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...
Table 35: Ethernet PHY interface connections
USB3 Interface
On the TEB0911 board two USB3 Superspeed ports are available to the user, which are downward compatible to USB2 Highspeed.
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The 4-port USB3 hub is connected to the Zynq MPSoC's PS GTR bank, the USB2 PHY is connected to the PS MIO bank 502:
...
- B505_TX1_P
- B505_TX1_N
- B505_RX1_P
- B505_RX1_N
...
PS GTR bank 505
Pins:
- PS_MGTRTXP1_505, Y29
- PS_MGTRTXN1_505, Y30
- PS_MGTRRXP1_505, AA31
- PS_MGTRTXN1_505, AA32
...
- USB0_D_P
- USB0_D_N
...
USB2 PHY U15
Pins: 18,19
...
- USB3_RXDN1_D_P
- USB3_RXDN1_D_N
- USB3_TXDN1_D_P
- USB3_TXDN1_D_N
- USB3_RXDN2_D_P
- USB3_RXDN2_D_N
- USB3_TXDN2_D_P
- USB3_TXDN2_D_N
...
2-port USB3 A / RJ-45 connector
(stacked) J13
...
- USB2_DN1_D_P
- USB2_DN1_D_N
- USB2_DN2_D_P
- USB2_DN2_D_N
...
2-port USB3 A / RJ-45 connector
(stacked) J13
...
- USBH_SDA
- USBH_SCL
...
Configuration EEPROM U5,
8-channel I²C-switch U37
...
EEPROM U5 is configuration and
parameter memory of USB3 hub U4
...
- USBH_MODE0,
- USBH_MODE1
- USBH_RST
...
SC CPLD U27, bank 2
Pins: Y17, Y16, Y15
...
- USB0_STP
- USB0_NXT
- USB0_DIR
- USB0_CLK
- USB0_DATA0 ... USB0_DATA7
...
PS bank 502
Pins: MIO52 ... MIO63
...
-
...
- USB0_D_P
- USB0_D_N
...
USB3 Hub U4
Pins: 71,72
...
USB0_RST
...
SC CPLD U27, bank 4
...
-
Table 36: USB3 signals and interfaces
SFP+ Interface
The TEB0911 board provides the high speed MGT interface connectors "SFP+" (Enhanced small form-factor pluggable) with data transmission rates up to 10 Gbit/s.
Block diagram below shows the dependencies between the implied devices which establish the SFP+ interface:
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
Figure X: SFP+ interface
...
Signal Schematic Name
...
SFP+ J9A
...
- B129_TX3_P
- B129_TX3_N
- B129_RX3_P
- B129_RX3_N
...
GTH bank 129
Pins:
- MGTHTXP3_129, G31
- MGTHTXN3_129, G32
- MGTHRXP3_129, F33
- MGTHRXN3_129, F34
...
- SFP0_SDA
- SFP0_SCL
...
SFP0_RS0
...
I/O Port Expander on
same I²C line as
SFP0-I²C-interface
...
SFP+ J9B
...
- B129_TX2_P
- B129_TX2_N
- B129_RX2_P
- B129_RX2_N
...
GTH bank 129
Pins:
- MGTHTXP2_129, H29
- MGTHTXN2_129, H30
- MGTHRXP2_129, H33
- MGTHRXN2_129, H34
...
Multi gigabit highspeed
data lane
...
- SFP1_SDA
- SFP1_SCL
...
I/O Port Expander on
same I²C line as
SFP0-I²C-interface
...
Table 37: SFP+ signals and interfaces
SSD Interface
On the TEB0911 UltraRack board one SSD interface is available provided by a NGFF (Next Generation Form Faktor) M.2 socket (Key M) which supports data transmission rates for PCIe3, SATA3 and USB3 interfaces.
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Figure X: SSD interface
...
Signal Schematic Name
...
M.2-NGFF
PCIe Socket
U2
...
- B505_TX0_P
- B505_TX0_N
- B505_RX0_P
- B505_RX0_N
...
PS GTR bank 505
Pins:
- PS_MGTRTXP0_505, AB29
- PS_MGTRTXN0_505, AB30
- PS_MGTRRXP0_505, AB33
- PS_MGTRTXN0_505, AB34
...
- SSD_RCLK_P
- SSD_RCLK_N
...
SSD1_LED
...
Table 38: SSD signals and interfaces
DisplayPort Interface
The TEB0911 board provides the high speed DisplayPort interface for visual output. The DisplayPort is connected with two transmit LVDS-pairs of bank 505 PS GTR lanes. Additionally the auxiliary transmit line is established by the SC CPLD in conjunction with a LVDS Line Driver/Receiver.
...
| draw.io Diagram | ||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
...
Follwowing table contains a brief description of the MGT lanes and control and status signals of the DisplayPort interface:
...
Signal Schematic Name
...
DisplayPort
Connector J12
...
- B505_TX2_P
- B505_TX2_N
- B505_TX3_P
- B505_TX3_N
...
PS GTR bank 505
Pins:
- PS_MGTRTXP2_505, W31
- PS_MGTRTXN2_505, W32
- PS_MGTRTXP3_505, V29
- PS_MGTRTXN3_505, V30
...
- DP_TX_AUX_P
- DP_TX_AUX_N
...
Convert signal from single ended to LVDS
Single ended signals: 'DP_AUX_TX', 'DP_AUX_RX',
SC CPLD U27, bank 2, pins AA14, AB12
...
DP_TX_HPD
...
Table 39: DisplayPort signals and interfaces
DDR4 Memory Socket
On the TEB0911 board there is a DDR4 memory interface with a 64-bit databus width available for SO-DIMM modules.
...
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
...
Following table gives an overview about the I/O signals of the DDR4 SDRAM memory interface:
...
Signal Schematic Name
...
DDR4 SO-DIMM
Socket U13
...
- DDR4-CLK0_P
- DDR4-CLK0_N
- DDR4-CLK1_P
- DDR4-CLK1_N
...
- DDR4-DQS0_P
- DDR4-DQS0_N
- ...
- DDR4-DQS8_P
- DDR4-DQS8_N
...
address range configuration on I²C bus
...
- DDR4-SCL
- DDR4-SDA
...
Table 40: DDR4 64-bit memory interface signals and pins
Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s, which also depends on the used SO-DIMM module.
CAN Interface
The TEB0911 board provides a CAN interface, the CAN transceiver is connected and operated by the SC CPLD:
...
| draw.io Diagram | ||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
Figure X: CAN interface
...
D-SUB 9-pin
male connector
J3
...
6-pin male header
J15
...
Table 41: CAN interface signals and pins
SD Card Interface
The SD Card interface of the TEB0911 board is routed via SD IO interface to the PS MIO bank 501 of the Zynq Ultrascale+ MPSoC (3.3V VCCO). The SC CPLD U27 controls the load switch Q3 to enable the card sockets J11 with signal 'SD_EN', bank 2, pin U11. The "Card Detect" and "Write Protect" signal are also routed to the SC CPLD:
...
The SD Card socket have following signal and pin assignment:
...
SD Card
Socket J11
...
PS bank 501
Pins: MIO46 ... MIO51
...
Table 42: SD Card interface signals and connections
4-Wire PWM FAN Connectors
The TEB0911 offers 3x 4-wire PWM FAN connectors for optional cooling fans controlled by SC CPLD U27:
| draw.io Diagram | ||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
...
Fan Connector
J2
...
Fan Connector
J23
...
Fan Connector
J33
...
Table 43: 4-wire PWM fan connectors signals and pins
PLL Clock Interfaces
The programmable 10-output reference clock generator U17 can be accessed through its I²C interface to be programed. The I²C interface is connected to the Zynq MPSoc via I²C switch U13 and to pin header J22.
With the SMA Coaxial connector J25 the clock generator can be supplied with an external clock signal.
...
Pin Header
J22
...
SMA Coax
J25
...
Table 44: Clock generator Si5345A external interfaces
On-board Peripherals
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System Controller CPLD
The TEB0911 UltraRack is equipped with one System Controller CPLDs - Lattice Semiconductor LCMXO2-7000HC (MachXO2 Product Family) with the schematic designators U27. The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module. The functionalities and configuration of the pins depend on the CPLDs' firmware. The documentations of the firmware of SC CPLD U27 contains detailed information on this matter.
The Sytem Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO and PL pins. The signals of these pins are forwarded by the SC CPLD to control some of the on board peripherals.
Following block diagram visualizes the connection of the SC CPLDs with the Zynq Ultrascale+ MPSoC via PS MIO pins and singled ended PL pins:
...
| anchor | Figure X |
|---|---|
| title | Figure X: I/O's connecting Zynq MPSoC and SC CPLD |
...
For detailed information about the current function of the MIO-pin in conjunction with the SC CPLD, the internal signal assignment and implemented logic, refer to the Wiki reference page of the SC CPLD firmware of this board or into the bitstream file of the SC CPLD.
...
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For the detailed function of the pins and signals, the internal signal assignment and implemented logic, look to the Wiki reference page SC CPLD of this module or into the bitstream file of the SC CPLD.
Add link to the Wiki reference page of the SC CPLD, if available.
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High-speed USB2 ULPI PHY
USB2 PHY U15 is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator U16.
...
SC CPLD U27, bank 4, Pin: M2
...
Table 45: USB PHY interface connections
4-port USB3 Hub
On the TEB0911 board there are to 2 USB3 Super Speed ports available, which are also downward compatible to USB2 High Speed ports. The USB3 ports are provided by Cypress Semiconductor CYUSB3324 4-port USB3 Hub controller U4. The pin-strap configuration option of the USB3 Hub is disabled, so this controller gets the configuration data and parameter from the configuration EEPROM U5. The I²C interface of the EEPROM and the controller are also accessible by the Zynq Ultrascale+ MPSoC through I²C switch U37.
On the Upstream-side, this controller is connected to the MGT1 lane of MPSoC's PS GT bank 505 to establish the USB3 data lane. For the USB2 interface, the controller is connected to the on-board USB2 PHY U15. The USB2 PHY is connected via ULPI interface (MIO pins 52..63) to MPSoC's MIO bank.
The USB3 Hub controller has also an ARM Cortex-M0 controller integrated, refer to the data sheet for further features and programmable options.
Gigabit Ethernet PHY
On-board Gigabit Ethernet PHY U20 is provided with Marvell Alaska 88E1512. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The 125MHz PHY output clock (PHY_CLK125M) is routed to System Controller CPLD U27, bank 4, pin K2.
8-Channel I²C Switches
All on-board and on-module peripherals with accessible I²C interface are muxed to the I²C interface of the Zynq Ultrascale+ MPSoC as master.
For this purpose, the TEB0911 board is equipped with two 8-channel I²C switches provided by TCA9548A from Texas Instruments, together creating up to 16 switched I²C channels.
Refer to the data sheet of the TCA9548A chip how to address and and transmit data to the I²C slave devices through this switches.
The on-board I2C bus works with reference voltage 3.3V, it is connected to the MPSoC I2C interface via PS MIO bank (pins MIO38, MIO39) and configured as master.
...
Table 46: MIO-pin assignment of the module's I2C interface
...
I2C addresses (7 bit without read/write-bit) for on-board slave devices are listed in the table below:
...
Table 46: On-board peripherals' I2C-interfaces device slave addresses
Configuration EEPROMs
The TEB0911 carrier board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip and all have I²C interfaces:
...
Table 47: On-board configuration EEPROMs overview
CAN FD Transceiver
On-board CAN FD (Flexible Data Rate) transceiver U48 is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.
The transceiver is connected to System Controller CPLD U27, means it works on this interface with 3.3V VCCIO. The logical signal processing of the CAN interface depends on the current firmware ot the SC CPLD.
On-board Flash Memory
On-board QSPI flash memory U24 and U25 on the TEB0911 board is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity each. The QSPI Flash memory ICs are connected to the PS MIO bank (Dual QSPI MIO0 ... MIO12) of the Zynq Ultrascale+ MPSoC. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the Zynq MPSoC allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
The TEB0911 board is also equipped with embedded MMC memory connected to the PS MIO bank (MIO13 ... MIO23) of the Zynq Ultrascale+ MPSoC. The memory is provided by MTFC4GACAJCN-4M IT from Micron Technology. It has a memory density of 32 Gbit (4 GByte) and is sectored into 8 banks a 4 Gbit.
...
dual parallel booting possible, 64 MByte total QSPI Flash memory
connected via Dual QSPI MIO0 ... MIO12
...
Quad SPI Flash memory ICs U24 and U25 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.
eMMC Flash memory IC U25 is connected to Zynq MPSoC by pins MIO13 ... MIO23.
...
| Note |
|---|
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
Oscillators
The TEB0911 board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:
...
- XAXB_P
- XAXB_N
...
SiTime SiT8008AI oscillator, U87
optional, not equipped
...
DSC1123 oscillator, U92
optional, not equipped
...
- B505_CLK3_P
- B505_CLK3_N
...
Table 50: Reference clock signal oscillators
Programmable Clock Generator Si5338A
There is a Si5338A U12, Silicon Labs I2C programmable quad PLL clock generator on-board to generate various reference clocks for the Zynq MPSoC MGT banks and on-board peripherals.
...
IN1
...
IN3
...
Reference input clock
...
IN4
...
IN5
...
-
...
CLK0A
...
SSD_RCLK_P
...
NGFF M.2 PCIe socket (Key M),
dedicated as SSD interface
...
PS GTR Bank 505 Lane 2, dedicated for DisplayPort,
...
PS GTR Bank 505 Lane 1, dedicated for USB3 interface
...
B505_CLK0_P
...
PS GTR Bank 505 Lane 0, dedicated for SSD interface
...
Table 51: Programmable quad PLL clock generator inputs and outputs
Programmable Clock Generator Si5345A
Following table shows on-board Silicon Labs I2C programmable Si5345A U17 10-output programmable PLL reference clock generator inputs and outputs:
...
-
...
-
...
not used
...
not used
...
GTH bank 229 reference clock input
...
CLK2_P
...
GTH bank 230 reference clock input
...
Differential reference clock input to
PLL clock generator U12
...
Table 52: Programmable 10-output PLL clock generator inputs and outputs
Note: The PLL clock generator U17 can be reseted by the pin 'PLL_RST', which is connected to SC CPLD U27, bank 4 pin L4 with low active logic.
On-board LEDs
The TEB0911 board is equipped with several LEDs to signal current states and activities.
...
Reflects inverted DONE signal. ON when FPGA is not configured,
OFF as soon as PL configuration is finished.
...
LED is on if all USB3 and USB2 ports are in the suspend state and is
off when one of the ports comes out of the suspend state.
...
functionality depends on the current firmware of the SC CPLD U27
refer to the documentation
section: LED
...
Table 53: On-board LEDs
User Buttons
There are two switch buttons available to the user connected to the SC CPLD U27:
...
high active logic, connected to 3V3SB,
functionality depends on the current firmware of the SC CPLD U27
refer to the documentation
...
Table 54: On-board switch buttons
Configuration DIP-switches
There are two 4-bit DIP-witches S3 and S4 present on the TEB0911 board to configure options and set parameters. The following section describes the functionalities of the particular switches.
Table below describes the functionalities of the switches of DIP-switches S3 and S4 at their each positions:
...
Positions
ON: SC CPLD's JTAG enabled
OFF: SC CPLD's JTAG disabled
...
SC_SW1
...
TEB0911 CPLD Firmware Documentation
Section: Boot Mode
...
SC_SW2
...
Table 55: DIP-switch S3 and S4 functionality description
Power and Power-On Sequence
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Power Consumption
The maximum power consumption of the board mainly depends on the design running on the FPGA.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
...
Table : Typical power consumption, *to Be Determined soon with reference design setup.
Power supply with minimum current capability of ?? A for system startup is recommended.
The TEB0911 UltraRack board is equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.
This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq UltraScale+ MPSoC has multiple power domains, whereby each power domain requires its own particular on-board DC-DC converters.
The Processing System contains three Power Domains:
- Battery Power Domain (BBRAM and RTC)
- Full-Power Domain (Application Processing Unit, DDR Controller, Graphics Processing Unit and High-Speed Connectivity)
- Low-Power Domain (Real-Time Processing Unit, Security and Configuration Unit, Platform Management Unit, System Monitor and General Connectivity)
- Programmable Logic (PL)
Power Distribution Dependencies
There are following dependencies how the initial 24V voltage from the main power jack J34 is distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:
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| Warning |
|---|
| To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
Power-On Sequence
The TEB0911 UltraRack board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.
On the TEB0911 UltraRack board following Power Domains will be powered up in a certain sequence with by enable and power-good signals of the DC-DC converters, which are controlled by the System Controller CPLD U27:
- Low-Power Domain (LPD)
- Programmable Logic (PL) and Full-Power Domain (FPD)
- GTH, PS GTR transceiver and DDR memory
Hence, those three power instances will be powered up consecutively and the Power-Good-Signals of the previous instance is asserted.
Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter control signals (Enable, Power-Good), which will power-up in descending order as listed in the blocks of the diagram.
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Figure : Module power-on diagram.
Temp core dc
Power Rails
NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.
...
Power Rail Name
...
B2B JM1 Pins
...
B2B JM2 Pins
...
Direction
...
VBAT_IN
...
Table : Module power rails
Bank Voltages
...
Bank
...
Voltage
...
Voltage Range
...
Table : Module PL I/O bank voltages
Variants Currently In Production
NB! Note that here we look at the module as a whole, so you just can't rely only on junction temperature or max voltage of particular SoC or FPGA chip on the module. See examples in the table below.
...
Operating Temperature
...
Table : Module variants
Technical Specifications
Absolute Maximum Ratings
...
Parameter
...
Units
...
Reference Document
...
VIN supply voltage
...
V
...
Storage temperature
...
°C
...
Table : Module absolute maximum ratings
| Note |
|---|
| Assembly variants for higher storage temperature range are available on request. |
Recommended Operating Conditions
...
Table : Module recommended operating conditions
| Note |
|---|
| Please check Xilinx datasheet ... for complete list of absolute maximum and recommended operating ratings. |
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Extended grade: 0°C to +85°C.
Industrial grade: -40°C to +85°C.
Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Physical Dimensions
Module size: ... mm × ... mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ... mm.
PCB thickness: ... mm.
Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.
All dimensions are given in millimeters.
Put mechanical drawings here...
Figure : Module physical dimensions drawing.
Revision History
Hardware Revision History
...
Notes
...
01
...
Prototypes
Table : Module hardware revision history
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Put picture of actual PCB showing model and hardware revision number here...
Figure : Module hardware revision number.
Document Change History
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Generate new entry:
1.add new row below first
2.Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number
3.Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description.
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Date
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Revision
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Contributors
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Description
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Table : Document change history
Disclaimer
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Overview
Content Tools