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The Trenz Electronic TEM0002-01 SmartBerry is an industrial-grade module  module based on Microsemi SmartFusion2 SoC.

Key Features

• Microsemi SmartFusion2 SoC FPGA
• 128MB DDR3 SDRAM
• On board power converters for all needed voltages.
• 40 pin header compatible to Raspberry Pi pinout.
• 4 x 12 pin PMOD
• Gigabit Ehernet PHY with RGMII interface

Additional assembly options are available for cost or performance optimization upon request.

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Figure 1: TEM0002-01 block diagram.

Main Components

Put top and bottom pics with labels of the real PCB here...

Table 1: TEM0002-01 main components.

1. Microsemi SmartFusion2 SoC FPGA
   
2. DDR3 SDRAM 128MB (1Gb)
3. Micro USB 2.0
4. USB to UART/FIFO (FTDI FT2232H)
5. EEPROM 4KBIT (M93C66-R)

Initial Delivery State

...

Storage device name

...

Content

...

Notes

...

..

...

..

...

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector JM..

...

MODE Signal State

...

High or open

...

SD Card

...

Low or ground

...

QSPI Interface

Table 2: Selecting power-on boot device.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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Board to Board (B2B) I/Os

I/O signals connected to the SoCs I/O bank and B2B connector: 

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Table x: General overview of PL I/O signals connected to the B2B connectors.

All PS MIO banks are powered by on-module DC-DC power rail. All PL I/O banks have separate VCCO input pins in the B2B connectors, valid VCCO should be supplied from the carrier board.

For detailed information about the pin out, please refer to the Pin-out Tables. 

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Table 1: TEM0002-01 main components.

1. Microsemi SmartFusion2 SoC FPGA, U2
2. USB to UART/FIFO (FTDI FT2232H), U3
3. Gigabit ETH Connector, J2
4. 4x  2x6 Pin PMOD, P1, P2, P3, P4
   
5. GPIO Pin Header Compatible to Raspberry Pi, J8
6. Micro USB 2.0, J1
7. EEPROM 4KBIT (M93C66-R), U6
8. 2x User Button, S4, S5
9. RGB LED, D3
10. LED red, D1 and green, D2
11. Live Probe Pins, J4
12. JTAG Select Jumper, J6
13. Board Power Header, J5
14. 1Gb DDR3/L SDRAM, U5
15. microSD Memory Card Connector, J3
16. Gigabit Ethernet PHY, U1

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector JM..

Table 2: Selecting power-on boot device.

Signals, Interfaces and Pins

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TO-DO (future):
If Vivado board part filesConnections and Interfaces or B2B Pin's which are availableaccessible forby this module, the standard configuration of the MIO pins by using this board part files should be mentioned here. This standard configuration of those pins are also apparent of the on-board peripherals of base-boards related to the module.
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MGT Lanes

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MGT lanes should be listed separately, as they are more specific than just general I/Os.  
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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

User
  -->

Board to Board (B2B) I/Os

I/O signals connected to the SoCs I/O bank and B2B connector: 

Table x: General overview of PL I/O signals connected to the B2B connectors.

All PS MIO banks are powered by on-module DC-DC power rail. All PL I/O banks have separate VCCO input pins in the B2B connectors, valid VCCO should be supplied from the carrier board.

For detailed information about the pin out, please refer to the Pin-out Tables. 

The configuration of the PS I/Os MIOx, MIOx ... MIOx, ... depend on the carrier board peripherals connected to these pins.

<!--
TO-DO (future):
If Vivado board part files are available for this module, the standard configuration of the MIO pins by using this board part files should be mentioned here. This standard configuration of those pins are also apparent of the on-board peripherals of base-boards related to the module.
  -->

MGT Lanes

<!--
MGT lanes should be listed separately, as they are more specific than just general I/Os.  
  -->

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Table x: MGT lanes.

Below are listed MGT banks reference clock sources.

Table x: MGT reference clock sources.

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JTAG access to the ... is provided through B2B connector .... 

Table 5: JTAG interface signals.

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Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Table x: System Controller CPLD I/O pins.

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Note that table column says "Signal Name", it should match the name used on the schematic.

Table x: Quad SPI interface signals and connections.

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Describe SD Card interface  shortly here if the module has one...

Table x: SD Card interface signals and connections.

...

On board Gigabit Ethernet PHY is provided with ...

Ethernet PHY connection

Table x: ...

USB Interface

USB PHY is provided with ...

Table x: ...

The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

On-board I²C devices are connected to MIO.. and MIO.. which are configured as I²C... by default. I²C addresses for on-board devices are listed in the table below:

...

Table x: I²C slave device addresses.

On-board Peripherals

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Components on the Module, like Flash, PLL, PHY...
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System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

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Put in link to the Wiki reference page of the firmware of the SC CPLD.
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DDR Memory

By default TE0xxx module has ... DDRx SDRAM chips arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

RTC - Real Time Clock

An temperature compensated Intersil ISL...

Programmable Clock Generator

There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

...

IN1

...

-

...

Not used.

...

IN3

...

Reference input clock.

...

IN4

...

IN5

...

-

...

CLK0A

...

CLK1_P

...

FPGA bank 45.

...

CLK0_P

...

FPGA bank 45.

...

for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

On-board I²C devices are connected to MIO.. and MIO.. which are configured as I²C... by default. I²C addresses for on-board devices are listed in the table below:

Table x: I²C slave device addresses.

On-board Peripherals

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Components on the Module, like Flash, PLL, PHY...
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System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

<!--
Put in link to the Wiki reference page of the firmware of the SC CPLD.
  -->

DDR Memory

By default TE0xxx module has ... DDRx SDRAM chips arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Table : Reference clock signals.

On-board LEDs

 Table : Programmable quad PLL clock generator inputs and outputs.

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

...

Table : Reference clock signals.

On-board LEDs

Table : On-board LEDs.

Power and Power-On Sequence

...

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table : Typical power consumption.

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NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.

Table : Module power rails.

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Bank Voltages

Table : Module PL I/O bank voltages.

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NB! Note that here we look at the module as a whole, so you just can't rely only on junction temperature or max voltage of particular SoC or FPGA chip on the module. See examples in the table below.

Table : Module variants.

Technical Specifications

Absolute Maximum Ratings

Table : Module absolute maximum ratings.

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Recommended Operating Conditions

Table : Module recommended operating conditions.

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Hardware Revision History

Table : Module hardware revision history.

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Table : Document change history.

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