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The Trenz Electronic TEM0002-01 SmartBerry with Raspberry Pi form factor, is an industrial-grade module based on Microsemi SmartFusion2 SoC (System on a Chip). The Module has 128MB DDR3 SDRAM, a Gigabit Ethernet PHY, Micro USB,   four PMODs and , a GPIO Pin header compatible to the Raspberry Pi pinout and a Micro USB to UART interface. SmartFusion2 combiens a 166 MHz Cortex-M3 core with 256 KByte Flash, 80 KByte SRAM  and a 12 kLUT FPGA Core Logic.

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Figure 1: TEM0002-01 block diagram.

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Table 1: Initial delivery state of programmable devices on the module.

Boot Process

The SmartBerry supports SD Card boot mode.

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MODE Signal State

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SD Card

Table 2: Selecting power-on boot device.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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I/Os

I/O signals connected to the SoCs I/O bank and B2B connector: 

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TO-DO (future):
If Vivado board part files are available for this module, the standard configuration of the MIO pins by using this board part files should be mentioned here. This standard configuration of those pins are also apparent of the on-board peripherals of base-boards related to the module.
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PMODs

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MGT lanes should be listed separately, as they are more specific than just general I/Os.  
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Table x: MGT lanes.

Below are listed MGT banks reference clock sources.

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Table x: MGT reference clock sources.

JTAG Interface

JTAG access to the ... is provided through B2B connector .... 

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JTAG Signal

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B2B Connector Pin

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Table 5: JTAG interface signals.

System Controller CPLD I/O Pins

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

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Table x: System Controller CPLD I/O pins.

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For the detailed function of the pins and signals, the internal signal assignment and implemented logic, look to the Wiki reference page SC CPLD of this module or into the bitstream file of the SC CPLD.
Add link to the Wiki reference page of the SC CPLD, if available.
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Quad SPI Interface

Following line is just an example, change it to your needs.

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

Note that table column says "Signal Name", it should match the name used on the schematic.

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Table x: Quad SPI interface signals and connections.

SD Card Interface

Describe SD Card interface  shortly here if the module has one...

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Table x: SD Card interface signals and connections.

Ethernet Interface

On board Gigabit Ethernet PHY is provided with ...

Ethernet PHY connection

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Table x: ...

USB Interface

USB PHY is provided with ...

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Table x: ...

The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

On-board I²C devices are connected to MIO.. and MIO.. which are configured as I²C... by default. I²C addresses for on-board devices are listed in the table below:

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Table x: I²C slave device addresses.

On-board Peripherals

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Components on the Module, like Flash, PLL, PHY...
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System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

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Put in link to the Wiki reference page of the firmware of the SC CPLD.
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DDR Memory

By default TE0xxx module has ... DDRx SDRAM chips arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

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25.000 MHz

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Table : Reference clock signals.

On-board LEDs

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U2-H5 Bank 7, U2-F6 Bank 7, U2-H6 Bank 7

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Table : On-board LEDs.

Power and Power-On Sequence

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If power sequencing and distribution is not so much, you can join both sub sections together
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Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

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Table : Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The on-board voltages of the TE07xx SoC module will be powered-up in order of a determined sequence after the external voltages '...', '...' and '...' are available. All those power-rails can be powered up, with 3.3V power sources, also shared. <-- What?

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Table x: MGT lanes.

JTAG Interface

JTAG access to the ... is provided through B2B connector .... 

Table 5: JTAG interface signals.

SD Card Interface

Table x: SD Card interface signals and connections.

Ethernet Interface

On board Gigabit Ethernet PHY is provided with ...

Ethernet PHY connection

Table x: ...

I2C Interface

On-board I²C devices are connected to MIO.. and MIO.. which are configured as I²C... by default. I²C addresses for on-board devices are listed in the table below:

Table x: I²C slave device addresses.

On-board Peripherals

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Components on the Module, like Flash, PLL, PHY...
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DDR Memory

TEM0002 has 1Gb industrial grade DDR3 SDRAM (U5) in a 16-bit wide memory bus providing total of 128 MBytes of on-board RAM.

The Datasheet notes 800 MHz clocking resulting in 1600 Mb/s data rate and timing specification of 11-11-11 (CL-T_RCD-T_RP).

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (J2) is provided by  Microsemi VSC8531 chip (U1). The Ethernet PHY RGMII interface is connected to Bank 6 of the Microsemi SOC. I/O voltage is fixed at 1.5V. The reference clock input of the PHY is supplied from an external 25.000000 MHz oscillator (U11).

Oscillators

The module has following reference clock signals provided by on-board oscillators:

Table : Reference clock signals.

In REV02, Y1 will be replaced by a 12MHz crystal.

On-board LEDs

Table : On-board LEDs.

Power and Power-On Sequence

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If power sequencing and distribution is not so much, you can join both sub sections together
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Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Table : Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

Power Distribution Dependencies

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