Page History

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Main Components

Photo shows similar TE0841-01

1. Xilinx Kintex UltraScale FPGA, U1
2. Ultra performance oscillator @25.000000 MHz, U3
3. 12A PowerSoC DC-DC converter (0.95V), U14
4. 12A PowerSoC DC-DC converter (0.95V), U7

5. Low-jitter precision LVDS oscillator @200.0000 MHz, U11

6. Low-dropout (LDO) linear regulator (MGTAVTT 1.20V), U8
7. Low-dropout (LDO) linear regulator (MGTAVCC 1.02V), U12
8. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
9. Samtec Razor Beam™ LSHM-150 B2B connector, JM2
10. Samtec Razor Beam™ LSHM-130 B2B connector, JM3
11. Programmable quad clock generator, U2
12. 64 MByte QSPI Flash, U6
13. 8 Gbit DDR4 SDRAM, U4
14. 8 Gbit DDR4 SDRAM, U5
15. System Controller CPLD, U18
16. Low-dropout (LDO) linear regulator (MGTAUX), U9
17. Ultra-low power low-dropout (LDO) regulator (VBATT), U19

Initial Delivery State

Table 1: TE0841-02 module initial delivery state of programmable on-board devices

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I/O signals connected to the SoCs I/O bank and B2B connector:

Table 2: General overview of FPGA's PL I/O signals connected to the B2B connectors

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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Table 3: FPGA to B2B connectors routed MGT lanes overview

Below are listed MGT banks reference clock sources:

Table 4: MGT reference clock sources

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JTAG access to the Xilinx Kintex UltraScale FPGA is available through B2B connector JM2.

Table 5: JTAG interface signals

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Special purpose pins are connected to the System Controller CPLD and have following default configuration:

Table 6: System Controller CPLD I/O pins

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Quad SPI interface is connected to the FPGA configuration bank 0.

Table 7: Quad SPI interface signals and connections

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On-module I²C interface is routed  from PL bank 65 I/O pins (PLL_SCL and PLL_SDA) to the I²C interface of Si5338 PLL quad clock generator U2, also two further pins of bank 65 can be used as external I²C interface of the modue:

Table 8: I²C slave device addresses

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There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

 Table 9: Programmable quad PLL clock generator inputs and outputs, *PCB REV01 is not programmed

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The FPGA module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

Table 10: Reference clock signals

On-board LEDs

Table 11: On-board LEDs

Power and Power-On Sequence

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Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 12: Typical power consumption

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See also Xilinx datasheet DS892 for additional information. User should also check related base board documentation when intending base board design for TE0841 module.

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Power Rails

Table 13: Module power rails

Bank Voltages

Table 14: Module PL I/O bank voltages

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See also the current available variants on the Trenz Electronic shop page

Technical Specifications

Absolute Maximum Ratings

Table 16: Module absolute maximum ratings

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Recommended Operating Conditions

Table 17: Module recommended operating conditions

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Hardware Revision History

Table 18: Module hardware revision history

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