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  1. Xilinx ZYNQ UltraScale+ XCZU9EG MPSoC, U1
  2. Low-power programmable oscillator @ 33.333333 MHz (PS_CLK), U32
  3. Red LED (DONE), D1
  4. 256Mx16 DDR4-2400 SDRAM, U12
  5. 256Mx16 DDR4-2400 SDRAM, U9
  6. 256Mx16 DDR4-2400 SDRAM, U2
  7. 256Mx16 DDR4-2400 SDRAM, U3
  8. 12A PowerSoC DC-DC converter, U4
  9. Quartz crystal, Y1
  10. Low-power programmable oscillator @ 25.000000 MHz (IN0 for U5), U25
  11. 10-channel programmable PLL clock generator, U5
  12. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
  13. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
  14. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
  15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
  16. Quartz crystal, Y2
  17. 256 Mbit serial NOR Flash memory, U7
  18. 256 Mbit serial NOR Flash memory, U17


Initial Delivery State

 Storage Device Name

Content

Notes

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor.

SPI Flash Quad Enable bit

Programmed

-

SPI Flash main array

Not programmed

-

eFUSE USER

Not programmed

-

eFUSE Security

Not programmed

-
Si5345A OTP NVMNot programmed-

Table 1: Initial delivery state of programmable devices on the module

...

The boot device and mode of the Zynq UltraScale+ MPSoC can be selected via 4 dedicated pins accessible on B2B connector J2:

Boot Mode PinB2B Pin
PS_MODE0J2-109
PS_MODE1J2-107
PS_MODE2J2-105
PS_MODE3J2-103

Table 2: Boot mode pins on B2B connector J2.


Following boot modes are possible on the TE0808 UltraScale+ module by generating the corresponding 4-bit code by the pins PS_MODE0 ... PS_MODE3 (little-endian alignment):

Boot ModeMode Pins [3:0]MIO LocationDescription
JTAG0x0JTAGDedicated PS interface.
QSPI320x2MIO[12:0]

Configured on module with dual QSPI Flash Memory.

32-bit addressing.
Supports single and dual parallel
configurations.
Stack and dual stack is not
supported.

SD00x3MIO[25:13]Supports SD 2.0.
SD10x5MIO[51:38]Supports SD 2.0.
eMMC_180x6MIO[22:13]Supports eMMC 4.5 at 1.8V.
USB 00x7MIO[52:63]Supports USB 2.0 and USB 3.0.
PJTAG_00x8MIO[29:26]PS JTAG connection 0 option.
SD1-LS0xEMIO[51:39]

Supports SD 3.0 with a required SD 3.0 compliant level shifter.

Table 3: Selectable boot modes by dedicated boot mode pins.

...

Following table lists the I/O-bank signals, which are routed from the MPSoC's PL and PS banks as LVDS pairs or single ended I/O's to the B2B connectors.

BankTypeB2B Connector
Schematic Names / Connector Pins
I/O Signal Count
LVDS Pairs
VCCO 24
Bank VoltageNotes
47HDJ3

B47_L1_P ... B47_L12_P
B47_L1_N ... B47_L12_N

24 single-ended I/Os
or 12 LVDS pairs

VCCO47


pins J3-43, J3-44

VCCO max. 3.3V


usable as single

48HDJ324 single-ended I/Os or 12 LVDS pairs
48HDJ3

B48_L1_P ... B48_L12_P
B48_L1_N ... B48_L12_N

24 I/Os12

VCCO48
pins J3-15, J3-16

VCCO max. 3.3V
usable as single-ended I/Os

64HPJ4

B64_L1_P ... B64_L24_P
B64_L1_N ... B64_L24_N

B_64_T0 ... B_64_T3

VCCO48

VCCO max. 3.3V

64HPJ452 single-ended
52
I/O's
or 24

VCCO64
pins J4-58, J4-106

VCCO max. 1.8V
usable as single-ended I/Os

65HPJ4

B65_L1_P ... B65_L24_P
B65_L1_N ... B65_L24_N

B_65_T0 ... B_65_T3

52 I/Os24

VCCO65
pins J4-69, J4-105

VCCO max. 1.8V
usable as single-ended I/Os

66HPJ1

B66_L1_P ... B66_L24_P
B66_L1_N ... B66_L24_N

B_66_T0 ... B_66_T3

48 I/Os24
LVDS pairs

VCCO64

VCCO max. 1.8V

65HPJ452 single-ended I/Os or 24 LVDS pairs

VCCO65

VCCO66
pins J1-90, J1-120

VCCO max. 1.8V


usable as single

66HPJ152 single-ended I/Os or 24 LVDS pairs

VCCO66

VCCO max. 1.8V

500MIOJ3
MIO13 ... MIO25
13 I/Os
-
PS_1V8User configurable I/Os on B2B
501MIOJ3
MIO26 ... MIO51
26 I/Os
-
PS_1V8User configurable I/Os on B2B
502MIOJ3
MIO52 ... MIO77
26 I/Os
-
PS_1V8User configurable I/Os on B2B

Table 4: B2B connector pin-outs of available PL and PS banks of the TE0807-01 SoM.

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The Xilinx Zynq UltraScale+ MPSoC device used on the TE0807 module has 20 high-speed data lanes (Xilinx GTH / GTR transceiver). All of them are wired directly to B2B connector. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

BankTypeLaneSignal NameB2B PinFPGA Pin
228GTH0
  • B505_RX0_P
  • B505_RX0_N
  • B505_TX0_P
  • B505_TX0_N
  • JM3-26
  • JM3-28
  • JM3-25
  • JM3-27
  • PS_MGTRRXP0_505, F27
  • PS_MGTRRXN0_505, F28
  • PS_MGTRTXP0_505, E25
  • PS_MGTRTXN0_505, E26
1


2


3


229GTH0
  • B505_RX1_P
  • B505_RX1_N
  • B505_TX1_P
  • B505_TX1_N
  • JM3-20
  • JM3-22
  • JM3-19
  • JM3-21
  • PS_MGTRRXP1_505, D27
  • PS_MGTRRXN1_505, D28
  • PS_MGTRTXP1_505, D23
  • PS_MGTRTXN1_505, D24
1


2


3


230GTH0
  • B505_RX2_P
  • B505_RX2_N
  • B505_TX2_P
  • B505_TX2_N
  • JM3-14
  • JM3-16
  • JM3-13
  • JM3-15
  • PS_MGTRRXP0_505, B27
  • PS_MGTRRXN0_505, B28
  • PS_MGTRTXP0_505, C25
  • PS_MGTRTXN0_505, C26
1


2


3


128GTH0
  • B505_RX3_P
  • B505_RX3_N
  • B505_TX3_P
  • B505_TX3_N
  • JM3-8
  • JM3-10
  • JM3-7
  • JM3-9
  • PS_MGTRRXP1_505, A25
  • PS_MGTRRXN1_505, A26
  • PS_MGTRTXP1_505, B23
  • PS_MGTRTXN1_505, B24
1


2


3


505GTR0


1


2


3


Table 4: MGT lanes


There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

Clock signalBankSourceFPGA PinNotes
B505_CLK0_P505B2B, JM3-31PS_MGTREFCLK0P_505, F23Supplied by the carrier board
B505_CLK0_N505B2B, JM3-33PS_MGTREFCLK0N_505, F24Supplied by the carrier board
B505_CLK1_P505U10, CLK2APS_MGTREFCLK1P_505, E21On-board Si5338A
B505_CLK1_N505U10, CLK2BPS_MGTREFCLK1N_505, E22On-board Si5338A
B505_CLK2_P505N/APS_MGTREFCLK2P_505, C21Not connected
B505_CLK2_N505N/APS_MGTREFCLK2N_505, C22Not connected
B505_CLK3_P505U10, CLK1APS_MGTREFCLK3P_505, A21On-board Si5338A
B505_CLK3_N505U10, CLK1BPS_MGTREFCLK3N_505, A22On-board Si5338A

Table 5: MGT reference clock sources

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JTAG access is provided through the MPSoC's PS configuration bank 503 with bank voltage PS_1V8.

JTAG SignalB2B Connector Pin
TCKJ2-120
TDIJ2-122
TDOJ2-124
TMSJ2-126

Table 4: B2B connector pin-out of JTAG interface.

...

For further information about the particular control signals and how to use and evaluate them, refer to the  Xilinx Zynq UltraScale+ MPSoC TRM and UltraScale Architecture Configuration - User Guide.

SignalB2B Connector PinFunction
DONEJ2-116PL configuration completed.
PROG_BJ2-100PL configuration reset signal.
INIT_BJ2-98PS is initialized after a power-on reset.
SRST_BJ2-96System reset.
MODE0 ... MODE3J2-109/J2-107/J2-105/J2-103

4-bit boot mode pins.

For further information about the boot modes refer to the Xilinx Zynq UltraScale+ MPSoC TRM section 'Boot and Configuration'.

ERR_STATUS / ERR_OUTJ2-86 / J2-88

ERR_OUT signal is asserted for accidental loss of power, an error, or an exception in the MPSoC's Platform Management Unit (PMU).

ERR_STATUS indicates a secure lock-down state.

PUDC_BJ2-127Pull-up during configuration (pulled-up to PL_1V8).

Table 5: B2B connector pin-out of MPSoC's PS configuration bank.

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The Xilinx Zynq UltraScale+ MPSoC provides differential pairs for analog input values. The pins are exposed to B2B-connector J2.

SignalB2B Connector PinFunction
V_P, V_NJ2-113, J2-115System Monitor
DX_P, DX_NJ2-119, J2-121Temperature-sensing diode pins

Table 6: B2B connector pin-out of analog input pins

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Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.

MIOSignal NameU7 Pin
MIOSignal NameU17 Pin
0SPI Flash CLKB2
7SPI Flash CS
C2
1SPI Flash IO1
D2
8SPI Flash IO0
D3
2SPI Flash IO2
C4
9SPI Flash IO1
D2
3SPI Flash IO3D4
10SPI Flash IO2
C4
4SPI Flash IO0
D3
11SPI Flash IO3D4
5SPI Flash CS
C2
12SPI Flash CLK
B2

Table 7: PS MIO pin assignment of the Quad SPI Flash memory ICs.

Default PS MIO Mapping

PS MIOFunctionB2B PinConnected toPS MIOFunctionB2B PinConnected to
0SPI0-U7-B2, CLK40..45--Not connected
1SPI0-U7-D2, DO/IO1
46SDJM1-17B2B, SD_DAT3
2SPI0-U7-C4, WP/IO2
47SD

JM1-19

B2B, SD_DAT2
3SPI0-U7-D4, HOLD/IO348SD

JM1-21

B2B, SD_DAT1
4SPI0-U7-D3, DI/IO0 49SDJM1-23B2B, SD_DAT0
5SPI0- U7-C2, CS50SDJM1-25B2B, SD_CMD
6N/A-Not connected51SDJM1-27B2B, SD_CLK
7SPI1-U17-C2, CS52USB_PHY-U18-31, OTG-DIR
8SPI1-U17-D3, DI/IO053USB_PHY-U18-31, OTG-DIR
9SPI1-U17-D2, DO/IO154USB_PHY-U18-5, OTG-DATA2
10SPI1-U17-C4, WP/IO255USB_PHY-U18-2, OTG-NXT
11SPI1-U17-D4, HOLD/IO356USB_PHY-U18-3, OTG-DATA0
12SPI1-U17-B2, CLK57USB_PHY-U18-4, OTG-DATA1
13..20eMMC-U6, MMC-D0..D758USB_PHY-U18-29, OTG-STP
21eMMC-U6, MMC-CMD59USB_PHY-U18-6, OTG-DATA3
22eMMC-U6, MMC-CLKR60USB_PHY-U18-7, OTG-DATA4
23eMMC-U6, MMC-RST61USB_PHY-U18-9, OTG-DATA5
24ETH-U8, ETH-RST62USB_PHY-U18-10, OTG-DATA6
25USB_PHY-U18, OTG-RST

63

USB_PHY-U18-13, OTG-DATA7
26MIOJM1-95B2B, as PJTAG MIO possible64ETH-U8-53, ETH-TXCK
27MIOJM1-93B2B, as PJTAG MIO possible65..66ETH-U8-50..51, ETH-TXD0..1
28MIOJM1-99B2B, as PJTAG MIO possible67..68ETH-U8-54..55, ETH-TXD2..3
29MIOJM1-99B2B, as PJTAG MIO possible69ETH-U8-56, ETH-TXCTL
30MIOJM1-92B2B (UART RX)70ETH-U8-46, ETH-RXCK
31MIOJM1-85B2B (UART TX)71..72ETH-U8-44..45, ETH-RXD0..1
32MIOJM1-91B2B73..74ETH-U8-47..48, ETH-RXD2..3
33MIOJM1-87B2B75ETH-U8-43, ETH-RXCTL
34..37--Not connected76ETH-U8-7, ETH-MDC
38I2C-U10-12, SCL77ETH-U8-8, ETH-MDIO
39I2C-U10-19, SDA----

Table 8: TE0807-01 PS MIO mapping

...

The TE0808 SoM can be configured with max. 512 MByte Flash memory for configuration and operation.

 NameICDesignatorPS7MIONotes
SPI FlashN25Q256A11E1240EU7QSPI0MIO0 ... MIO5dual parallel booting possible, 32 MByte memory per Flash IC at standard configuration
SPI FlashN25Q256A11E1240EU17QSPI0MIO7 ... MIO12as above

Table 10: Peripherals connected to the PS MIO pins.

...

Following table illustrates on-board Si5345A programmable clock multiplier chip inputs and outputs:

InputConnected toFrequencyNotes
IN0On-board Oscillator (U25)25.000000 MHz-
IN1B2B Connector pins J2-4, J2-6 (differential pair)UserAC decoupling required on base
IN2B2B Connector pins J3-66, J3-68 (differential pair)UserAC decoupling required on base
IN3OUT9UserLoop-back from OUT9
OutputConnected toFrequencyNotes
OUT0B2B Connector pins J2-3, J2-1 (differential pair)UserDefault off
OUT1B230 CLK0UserDefault off
OUT2B229 CLK1UserDefault off
OUT3B228 CLK1UserDefault off
OUT4B505 CLK2UserDefault off
OUT5B505 CLK3UserDefault off
OUT6B128 CLK0UserDefault off
OUT7B2B Connector pins J2-7, J2-9 (differential pair)UserDefault off
OUT8B2B Connector pins J2-13, J2-15 (differential pair)UserDefault off
OUT9IN3 (Loop-back)UserDefault off
XA/XBQuartz (Y1)50.000 MHz-

Table 11: Programmable PLL clock generator input/output.

...

The Si5345A programmable clock generator's control interface pins are exposed to B2B connector J2. For further information refer to the Si5345A data sheet.

SignalB2B Connector PinFunction
PLL_FINCJ2-81Frequency increment.
PLL_LOLNJ2-85Loss of lock (active-low).
PLL_SEL0 / PLL_SEL1J2-93 / J2-87Manual input switching.
PLL_FDECJ2-94Frequency decrement.
PLL_RSTJ2-59

Device reset (active-low)

PLL_SCL / PLL_SDAJ2-90 / J2-92

I2C interface, external pull-ups needed for SCL / SDA lines.

I2C address in current configuration: 1101000b.

Table 12: B2B connector pin-out of Si5345A programmable clock generator.

...

The TE0808-04 SoM is equipped with two on-board oscillators to provide the Zynq's MPSoC's PS configuration bank 503 with reference clock signals.

ClockFrequencyBank 503 PinConnected to
PS_CLK33.333333 MHzP20MEMS Oscillator, U32
PS_PAD (RTC)32.768 kHzR22/R23Quartz crystal, Y2

Table 13: Reference clock-signals to PS configuration bank 503.

On-board LEDs

LED

ColorConnected toDescription and Notes
D1RedDONE signal (PS Configuration Bank 503)This LED goes ON when power has been applied to the module and
stays ON until MPSoC's programmable logic is configured properly.

Table 14: LED's description.

...

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power Input PinTypical Current
DCDCINTBD*
LP_DCDCTBD*
PL_DCINTBD*
PS_BATTTBD*

Table 15: Maximum current of power supplies. *to be determined soon with reference design setup.

...

The on-board voltages of the TE0808 TE0807 SoM will be powered-up in order of a determined sequence by activating the above-mentioned power rails and the Enable-Signals of the DC-DC converters. The on-board voltages will be powered up at three steps.

...

The control signals have to be asserted on the B2B connector J2, whereby some of the Power-Good signals need external pull-up resistors.

Enable-SignalB2B Connector PinMax. VoltageNote
Power-Good-SignalB2B Connector PinPull-up ResistorNote
EN_LPDJ2-1086VTPS82085SIL data sheet
LP_GOODJ2-1064K7, pulled up to LP_DCDC-
EN_FPDJ2-102DCDCINNC7S08P5X data sheet
PG_FPDJ2-1104K7, pulled up to DCDCIN-
EN_PLJ2-101PL_DCINleft floating for logic high
(drive to GND for logic low)

PG_PLJ2-104External pull-up needed (max. voltage GT_DCDC),
max. sink current 1 mA

TPS82085SIL /
NC7S08P5X data sheet

EN_DDRJ2-112DCDCINNC7S08P5X data sheet
PG_DDRJ2-1144K7, pulled up to DCDCIN-
EN_PSGTJ2-84DCDCINNC7S08P5X data sheet
PG_PSGTJ2-82External pull-up needed (max. 5.5V),
max. sink current 1 mA
TPS74801 data sheet
EN_GT_RJ2-95GT_DCDCNC7S08P5X data sheet
PG_GT_RJ2-91External pull-up needed (max. 5.5V),
max. sink current 1 mA
TPS74401 data sheet
EN_GT_LJ2-79GT_DCDCNC7S08P5X data sheet
PG_GT_LJ2-97External pull-up needed (max. 5.5V),
max. sink current 1 mA
TPS74801 data sheet
EN_PLL_PWRJ2-776VTPS82085SIL data sheet
PG_PLL_1V8J2-80External pull-up needed (max. 5.5V),
max. sink current 1 mA
TPS82085SIL data sheet

Table 16: Recommended operation conditions of DC-DC converter control signals.

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anchorFigure_5
titleFigure 5: TE0784-01 Voltage Monitor Circuit
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Power Rails

Power Rail Name

B2B J1 PinsB2B J2 PinsB2B J3 PinsB2B J4 Pins

Directions

Note
PL_DCIN151, 153, 157, 159---Input-
DCDCIN

-

154, 156, 158, 160,
153, 155, 157, 159

--Input-
LP_DCDC-138, 140, 142, 144--Input-
PS_BATT-125--Input-
GT_DCDC--157, 158, 159, 160-Input-
PLL_3V3--152-InputU5 (programmable PLL)
3.3V nominal input
SI_PLL_1V8--151-OutputInternal voltage level
1.8V nominal output
PS_1V8-99147, 148-Output

Internal voltage level
1.8V nominal output

PL_1V891, 121---Output

Internal voltage level
1.8V

nominal output

nominal output

DDR_1V2-135--Output

Internal voltage level
1.2V nominal output

VCCO47--43, 44-Input-
VCCO48--15, 16-Input-
VCCO64---58, 106Input-
VCCO65---69, 105Input-
VCCO6690, 120---Input-
DDR_1V2-135-OutputInternal voltage level
1.2V nominal output

Table 16: TE0807-01 power rails

Bank Voltages

BankTypeSchematic Name
/ B2B Connector Pins
VoltageReference Input VoltageVoltage Range
47HDVCCO47
, pins J3-43, J3-44
user-
max
1.2V to 3.3V
48HDVCCO48
, pins J3-15, J3-16
user-
max
1.2V to 3.3V
64HPVCCO64
, J4-58, J4-106
userVREF_64, pin J4-88
max
1.2V to 1.8V
65HPVCCO65
, J4-69, J4-105
userVREF_65, pin J4-15
max
1.2V to 1.8V
66HPVCCO66
, J1-90, J1-120
userVREF_66, pin J1-108
max
1.2V to 1.8V
500MIOPS_1V81.8V--
501MIOPS_1V81.8V--
502MIOPS_1V81.8V--
503CONFIGPS_1V81.8V--

Table 17: TE0807-01 I/O bank voltages

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Variants Currently In Production

Trenz shop TE0807 overview page
English pageGerman page

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Unit

Notes / Reference Document

PL_DCIN-0.37VTPS82085SIL / EN63A0QI data sheet
DCDCIN-0.37VTPS82085SIL / TPS51206 data sheet
LP_DCDC-0.34VTPS3106K33DBVR data sheet
GT_DCDC-0.37VTPS82085SIL data sheet
PS_BATT-0.52VXilinx DS925 data sheet
PLL_3V3-0.53.8VSi5345/44/42 data sheet
VCCO for HD I/O banks-0.53.4VXilinx DS925 data sheet
VCCO for HP I/O banks-0.52VXilinx DS925 data sheet
VREF-0.52VXilinx DS925 data sheet
I/O input voltage for HD I/O banks-0.55VCCO + 0.55VXilinx DS925 data sheet
I/O input voltage for HP I/O banks-0.55VCCO + 0.55VXilinx DS925 data sheet
PS I/O input voltage (MIO pins)-0.5VCCO_PSIO + 0.55VXilinx DS925 data sheet,
VCCO_PSIO 1.8V nominally

Receiver (RXP/RXN) and transmitter
(TXP/TXN) absolute input voltage

-0.51.2VXilinx DS925 data sheet

Voltage on input pins of
NC7S08P5X 2-Input AND Gate

-0.5VCC + 0.5VNC7S08P5X data sheet,
see schematic for VCC

Voltage on input pins (nMR) of
TPS3106K33DBVR Voltage Monitor, U41

-0.3VDD + 0.3V

TPS3106 data sheet,
VDD = LP_DCDC

"Enable"-signals on TPS82085SIL
(EN_PLL_PWR, EN_LPD)
-0.37VTPS82085SIL data sheet

Storage temperature (ambient)

-40

100

°C

ROHM Semiconductor SML-P11 Series data sheet

Table 18: Module absolute maximum ratings

...

Recommended Operating Conditions

ParameterMinMaxUnitNotes / Reference Document
PL_DCIN2.56VEN63A0QI / TPS82085SIL data sheet
DCDCIN3.16VTPS82085SIL / TPS51206PSQ data sheet
LP_DCDC2.53.6VTPS82085SIL / TPS3106 data sheet
GT_DCDC2.56VTPS82085SIL data sheet
PS_BATT1.21.5VXilinx DS925 data sheet
PLL_3V33.143.47VSi5345/44/42 data sheet
3.3V typical
VCCO for HD I/O banks1.143.4VXilinx DS925 data sheet
VCCO for HP I/O banks0.951.9VXilinx DS925 data sheet
I/O input voltage for HD I/O banks.-0.2VCCO + 0.2VXilinx DS925 data sheet
I/O input voltage for HP I/O banks-0.2VCCO + 0.2VXilinx DS925 data sheet
PS I/O input voltage (MIO pins)-0.2VCCO_PSIO + 0.2VXilinx DS925 data sheet,
VCCO_PSIO 1.8V nominally
Voltage on input pins of
NC7S08P5X 2-Input AND Gate
0VCCV

NC7S08P5X data sheet,
see schematic for VCC

Voltage on input pin 'MR' of
TPS3106K33DBVR Voltage Monitor, U41

0VDDV

TPS3106 data sheet,
VDD = LP_DCDC

Table 19: Recommended operating conditions

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Hardware Revision History

DateRevision

Notes

PCN LinkDocumentation Link
-01current available module revision-TE0807-01

Table 20: Hardware revision history table

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Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat

  • initial document

Table 21: Document change history

...