Page History

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• Xilinx Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA SoC
• Large number of configurable I/Os are provided via rugged HPC FMC connector
• Dual ARM Cortex-A9 MPCore
  • 1 GByte RAM (32-Bit wide DDR3)
  • 32 MByte QSPI Flash memory
  • 2 x Hi-Speed USB2 ULPI transceiver PHY
  • 2 x Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
  • 4 GByte eMMC (optional up to 64 GByte)
• 2 x MAC-address EEPROMs
• Optional 2x 64 MByte HyperFLASH or 2x 8 MByte HyperRAM (max 2x 32 MByte HyperRAM)
• Temperature compensated RTC (real-time clock)
• Si5338A programmable quad PLL clock generator for GTX transceiver clocks
• Plug-on module with 3 x 160-pin high-speed strips
  • 16 GTX high-performance transceiver
  • 2x GT transceiver clock inputs
  • 254 FPGA I/O's (125 LVDS pairs)
• On-board high-efficiency switch-mode DC-DC converters
• System management
• eFUSE bit-stream encryption
• AES bit-stream encryption
• Evenly-spread supply pins for good signal integrity
• User LED

...

• PCI Express 2.0 x8 card with maximum throughput of 4 GB/s
• FMC High Pin Count (HPC) connector
• 8 FPGA MGT lanes available on PCIe interface
• DDR3 SO-DIMM SDRAM socket
• 256-Mbit (32-MByte) Quad SPI Flash memory (for configuration and operation) accessible through:
  • FPGA
  • JTAG port (SPI indirect, bus width x4)
• External clock input via SMA coaxial connector
• 28 GTH transceivers, each with up to 13.1 Gbit/s data transmission rate
• FPGA configuration through:
  • JTAG connector
  • Quad SPI Flash memory
• Programmable quad clock generator

• TI LMK04828B ultra low-noise JESD204B compliant clock jitter cleaner

• On-board high-efficiency DC-DC converters
• Up to 202 FPGA I/O pins available on FMC connector (up to 101 LVDS pairs possible)
• System management and power sequencing
• AES bit-stream encryption
• eFUSE bit-stream encryption
• Xilinx Kintex UltraScale FPGA (XCKU035 or XCKU040)
• 2 banks of 1024 MByte DDR4 SDRAM, 32bit wide memory interface
• 512 Mbit (64 MByte) QSPI Flash
• 3 x Samtec Razor Beam LSHM B2B, 260 terminals total
  - 60 x HR I/Os
  - 84 x HP I/Os
  - 8 x GTH transceiver lanes (TX/RX)
  - 2 x MGT external clock inputs
• Clocking
  - Si5338 - 4 output PLLs, GT and PL clocks
  - 200 MHz LVDS oscillator
• All power supplies on-board, single power source operation
• Evenly spread supply pins for optimized signal integrity
• Size: 40 x 50 mm
• 3 mm mounting holes for skyline heat spreader
• Rugged for industrial applications
  
  
  

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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Main Components

1. Xilinx Kintex XC7K-2FBG676I FPGA SoC, U6
2. ANSI/VITA 57.1 compliant FMC HPC connector, J2

Block Diagram

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...

...

Main Components

...

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1. Xilinx Kintex XC7K-2FBG676I FPGA SoC, U6
2. ANSI/VITA 57.1 compliant FMC HPC connector, J2
3. Cooling fan 5VDC M1 (45X5MM, 0.7W, 1.06CFM), M1
4. PCIe x8 connector, J1
5. SO-DIMM socket, U2
6. 6-pin 12V power connector, J5
7. Step-down DC-DC converter @1.5V and @4V (LT LTM4676A), U3
8. Step-down DC-DC converter @1.0V (LT LTM4676A), U4
9. 256 Mbit Quad SPI Flash Memory (Micron N25Q256A), U12
10. 10x Green user LEDs, D1 ... D10
11. 4-wire PWM fan connector, J4
12. User button, S2
13. FPGA JTAG connector, J9
14. sd
15. sd
16. sd
17. sd
18. s
19. sd
20. sd
21. s
22. sd
23. sd
24. s
25. s
26. sd
27. sd
28. sd
29. sd
30. FPGA JTAG connector, J9
31. User button, S2
32. SO-DIMM socket, U2
33. Xilinx Virtex-7 XC7VX330T-2FFG1157C FPGA, U1
34. ANSI/VITA 57.1 compliant FMC HPC connector, J2
35. SMA coaxial connector for external clock input, J3
36. System Controller CPLD JTAG connector, J8
37. I²C connector for LT LTM4676 step-down DC-DC regulator, J10
38. IDC header for access to 5 x high-speed data lanes (LVDS pairs), J7
39. 4-wire PWM fan connector, J4
40. 6-pin 12V power connector, J5
41. Reference clock generator @10.0 MHz (P5146) , U11
42. LDO DC-DC regulator @3.3V (LMK_3V3) (TI TPS74901RGWR), U21
43. 256 Mbit Quad SPI Flash Memory (Micron N25Q256A), U12
44. Cooling fan 5VDC M1 (45X5MM, 0.7W, 1.06CFM)
45. System Controller CPLD (Lattice Semiconductor LCMXO2-1200HC), U5
46. , M1
47. PCIe x8 connector, J1
48. SO-DIMM socket, U2
49. 6-pin 12V power connector, J5Ultra low jitter clock synthesizer (TI LMK04828B), U9
50. Step-down DC-DC regulator converter @1.0V 5V and @4V (LT LTM4676LTM4676A), U4U3
51. Step-down DC-DC regulator converter @1.5V 0V (VCC1V5LT LTM4676A) (LT LTM4676, U3
52. I²C Programmable quad clock generator (Silicon Labs Si5338A), U13
53. 4A PowerSoC DC-DC converter @1.8V (Altera EN6347QI, U20
54. LDO DC-DC regulator @1.0V (MGTAVCC_FPGA) (TI TPS74401RGW), U18
55. LDO DC-DC regulator @1.2V (MGTAVTT_FPGA) (TI TPS74401RGW), U17
56. U4
57. 256 Mbit Quad SPI Flash Memory (Micron N25Q256A), U12
58. 10x Green user LEDs connected to FPGA, D1 ... D10
59. 4-wire PWM fan connector, J4
60. User button, S2
61. FPGA JTAG connector, J9
62. 4bit DIP switch, S1
63. I²C header for LTM4676A DC-DC converter, J10
64. System Controller CPLD JTAG header, J8
65. 1x Green LED connected to SC CPLD, D11
66. 2-pin 5V FAN header, J6
67. System Controller CPLD (Lattice Semiconductor LCMXO2-1200HC), U5
68. 6A PowerSoC DC-DC converter @FMC_VADJ (Altera EN5365QI), U7
69. 4A PowerSoC DC-DC converter 4A PowerSoC DC-DC converter @3.3V (3V3FMC) (Altera EN6347QI), U15
70. LDO converter @1.2V (MGTAVTT_FPGA) (TI TPS74401RGW), U17
71. LDO converter @1.0V (MGTAVCC_FPGA) (TI TPS74401RGW), U18
72. 4A PowerSoC DC-DC converter @1.8V (FMC_VADJ) (Altera EN6347QI), U7

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module

Boot Process

4 of the 7 boot mode strapping pins (MIO2 ... MIO8) of the Xilinx Zynq-7000 SoC device are hardware programmed on the board, 3 of them are set by the SC CPLD firmware. The boot strapping pins are evaluated by the Zynq device soon after the 'PS_POR' signal is deasserted to begin the boot process (see section "Boot Mode Pin Settings" of Xilinx manual UG585).

The TE0782 board is programmed in the SC CPLD firmware to boot initially from the on-board QSPI Flash memory U38. See section Bootmode in the TE0782 SC CPLD reference Wiki page.

The JTAG interface of the module is provided for storing the data to the QSPI Flash memory through the Zynq-7000 device.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

Zynq-7000 SoC's I/O banks signals connected to the B2B connectors:

By default the configuration mode pins M[2:0] of the FPGA are set to QSPI mode (Master SPI), hence the FPGA is configured from serial NOR flash at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the QSPI flash memory.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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FMC HPC Connector I/Os

I/O signals connected to the SoCs I/O bank and B2B connector:

Table 2: General overview of board to board FPGA's PL I/O signals connected to the FMC connector

For detailed information about the pin - out, please refer to the Pin-out tableTables.

MGT Lanes

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MGT Lanes

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The Xilinx Zynq-7000 SoC used on the TE0782 module has 16 MGT transceiver lanes. All of them are wired directly to B2B connectors J1 and J3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane with data transmission rates up to 12.5Gb/s per lane (Xilinx GTX transceiver). . Following table lists lane number, FPGA MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Table 3: MGT lanes

There are 2 clock sources for the GTX transceivers. MGT_CLK1 and MGT_CLK4 are connected directly to B2B connector J3 and J1, so the clock can be provided by the carrier board. Clocks MGT_CLK0, MGT_CLK3, MGT_CLK5 and MGT_CLK6 are provided by the on-board clock generator (U2). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

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Table 4: MGT reference clock sources

JTAG Interface

JTAG access to the Xilinx Zynq-7000 is provided through B2B connector J3.

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JTAG Signal

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B2B Connector Pin

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Table 5: Zynq JTAG interface signals

JTAG access to the LCMXO2-1200HC System Controller CPLD U14 is provided through B2B connector J3.

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JTAG Signal

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B2B Connector Pin

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Pin J3-136 'JTAGENB' of B2B connector J3 is used to access the JTAG interface of the SC CPLD. Set high to program the System Controller CPLD via JTAG interaface.

System Controller CPLD I/O Pins

Special purpose pins are connected to System Controller CPLD and have following default configuration:

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Bootmode Pins

currently configured in SC CPLD firmare to boot from QSPI Flash

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reset USB2 PHYs
U4 and U8

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Table 7: System Controller CPLD special purpose pins.

See also TE0782 CPLD reference Wiki page.

Default PS MIO Mapping

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Table 8: Zynq PS MIO mapping

Gigabit Ethernet

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Table 3: FPGA to B2B connectors routed MGT lanes overview

Below are listed MGT banks reference clock sources:

Table 4: MGT reference clock sources

JTAG Interface

JTAG access to the Xilinx Kintex UltraScale FPGA is available through B2B connector JM2.

Table 5: JTAG interface signals

System Controller CPLD I/O Pins

Special purpose pins are connected to the System Controller CPLD and have following default configuration:

Table 6: System Controller CPLD I/O pins

For detailed function of the pins and signals, the internal signal assignment and the implemented logic, look to the Wiki reference page of the module's SC CPLD or into its bitstream file.

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Quad SPI Interface

Quad SPI interface is connected to the FPGA configuration bank 0.

Table 7: Quad SPI interface signals and connections

I2C Interface

On-module I²C interface is routed  from PL bank 65 I/O pins (PLL_SCL and PLL_SDA) to the I²C interface of Si5338 PLL quad clock generator U2, also two further pins of bank 65 can be used as external I²C interface of the modue:

Table 8: I²C slave device addresses

On-board Peripherals

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System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

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DDR Memory

By default TE0841 module has two K4A8G165WB-BIRC DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 2 GBytes of on-module RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-module QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q512A11G1240E with 512-Mbit (64 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Programmable Clock Generator

There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

 Table 9: Programmable quad PLL clock generator inputs and outputs, *PCB REV01 is not programmed

Oscillators

The FPGA module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

Table 10

ETH1 PHY connection:

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Table 9: General overview of the Gigabit Ethernet1 PHY signals

ETH2 PHY connection:

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-

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Table 10: General overview of the Gigabit Ethernet2 PHY signals

USB Interface

The TE0782 is equipped with two USB PHY's USB3320 from Microchip (U4 (USB0) and U8 (USB1)). The ULPI interface of USB0 is connected to the Zynq PS USB0, ULPI interface of USB1 to Zynq PS USB1. The I/O Voltage is fixed at 1.8V.

The reference clock input of both PHY's is supplied from an on board 52MHz oscillator (U7).

USB0 PHY connection:

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Table 11: General overview of the USB0 PHY signals

USB1 PHY connection:

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Table 12: General overview of the USB1 PHY signals

I2C Interface

The on-board I²C components are connected to bank 35 pins L15 (I2C_SDA) and L14 (I2C_SCL).

I²C addresses for on-board components:

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Table 13: Address table of the I²C bus slave devices

Pin Definitions

Pins with names ending with _VRN and _VRP are connected to Zynq PL HP bank special purpose pins VRN/VRP and can be routed to DCI calibration resistors on the baseboard. Otherwise they are usable as general purpose I/Os.

Bank 35 has 100 ohm DCI calibration resistors installed, it is also possible to "borrow" the DCI calibration from bank 35 for banks 34 and 33. For more detailed information about the DCI check Xilinx documentation.

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U14) is provided by Lattice Semiconductor LCMXO2-1200HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.

See also TE0782 CPLD reference Wiki page.

eMMC Flash Memory

eMMC Flash memory device (U15) is connected to the Zynq PS MIO bank 500 pins MIO10..MIO15. eMMC chips MTFC4GMVEA-4M IT (Flash NAND-IC 2x 16 Gbit) is used with 4 GByte of memory density.

DDR3L Memory

By default TE0782-02 module has two 16-bit wide IM (Intelligent Memory) IM4G16D3FABG-125I DDR3L SDRAM (DDR3-1600 Speedgrade) chips (U10, U19) arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM.

Quad SPI Flash Memory

Two quad SPI compatible serial bus flash memory for FPGA configuration file storage is provided by Spansion S25FL256SAGBHI20 (U38) with 256 Mbit (32 MByte) memory density. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

Gigabit Ethernet PHYs

On-board Gigabit Ethernet PHYs (U18, U20) are provided by Marvell Alaska 88E1512. The Ethernet PHYs' RGMII interfaces are connected to the Zynq's PS MIO bank 501 and to PL bank 9. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of both PHYs is supplied from an on-board 25.000000 MHz oscillator (U11).

High-speed USB ULPI PHYs

Hi-speed USB ULPI PHYs (U4. U8) are provided with USB3320 from Microchip. The ULPI interfaces are connected to the Zynq PS USB0 and USB1 via MIO28..51, bank 501 (see also section USB interface). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U7).

MAC Address EEPROMs

Two Microchip 24AA025E48 serial EEPROMs (U22, U24) contain globally unique 48-bit node address, which are compatible with EUI-48(TM) specification. The devices are organized as two blocks of 128 x 8 Kbit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. The MAC address EEPROMS areaccessible over I²C bus (see also section I²C interface).

Configuration EEPROM

The TE0782 board contains one EEPROM (U26) for configuration and general user purposes. The EEPROMs is provided by Microchip 24LC128-I/ST with 128 KBit memory density, the EEPROM is areaccessible over I²C bus (see also section I²C interface).

Programmable Clock Generator

There is a Silicon Labs I²C programmable clock generator Si5338A (U2) chip on-board. It's output frequencies can be programmed using the I²C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.

A 25.000000 MHz oscillator (U3) is connected to the pin IN3 and is used to generate the output clocks. The output voltage of the oscillator is provided by the 1.8V power rail, thus making output frequency available as soon as 1.8V is present. All 4 of the Si5338 clock outputs are connected to the MGT banks of the Zynq device. It is possible to use the clocks connected to the GTR bank in the user's logic design. This is achieved by instantiating a IBUFDSGTE buffer in the design.

Once running, the frequency and other parameters can be changed by programming the device using the I²C bus connected between the FPGA (master) and clock generator (slave). For this, proper I²C bus logic has to be implemented in FPGA.

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External clock signal supply from B2B connector J3, pins J3-38 / J3-40

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IN3

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25.000000 MHz

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Fixed input clock signal from reference clock generator SiT8008BI-73-18S-25.000000E (U3)

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IN5

...

-

...

Not connected

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IN6

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-

...

-

...

reference clock 0 of Bank 112 GTX

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CLK1 A/B

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reference clock 1 of Bank 111 GTX

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CLK2 A/B

...

-

...

reference clock 0 of Bank 110 GTX

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Table 14: General overview of the on-board quad clock generator I/O signals

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

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Table 15: Reference clock signals

On-board LEDs

Table 11Table 16: On-board LEDs

Power and

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Power Supply

Power supply with minimum current capability of 4A for system startup is recommended.

Power Consumption

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Power

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 * TBD - To Be Determined soon with reference design setup.

Power Distribution Dependencies

The Trenz TE0782 SoM is equipped with two quad DC-DC voltage regulators to generate required on-board voltage levels 1V, 3.3V, 1.8V, 1.2V_MGT, 1V_MGT. Additional voltage regulators are used to generate voltages 1.5V, VTT, VTTREF and 1.8V_MGT.

The power supply voltage 'C3.3V' of System Controller CPLD of the SoM have to be externally supplied with 3.3V nominal.

There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

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-On Sequence

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Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 12: Typical power consumption

 * TBD - To Be Determined soon with reference design setup.

Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

Power Distribution Dependencies

Power-On Sequence

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Scroll Title
anchor Figure_43 title Figure 43: TE0782TE0841-02 Power -on Sequence Distribution Diagram
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111, 112, 123, 124, 135 136

169, 170, 171, 172

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See also Xilinx datasheet DS892 for additional information. User should also check related base board documentation when intending base board design for TE0841 module.

Power-On Sequence

The TE0841 SoM meets the recommended criteria to power up the Xilinx FPGA properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the FPGA chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Power Rails

Table 13: Module power rails

Bank Voltages

Table 18: Module power rails

Bank Voltages

Table 1914: Module Module PL I/O bank voltages

See Xilinx Zynq-7000 datasheet DS191 for the voltage ranges allowed.

Board to Board Connectors

The TE0782 SoM has three 160-pin double-row ASP-122952-01  Samtec connectors on the bottom side which mate with ASP-122953-01 Samtec connectors on the baseboard. Mating height is 5 mm.

Variants Currently In Production

Board to Board Connector

Variants Currently In Production

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See also the current available variants on the Trenz Electronic shop page

Technical Specifications

Absolute Maximum Ratings

Table 2016: Module absolute maximum ratings

Recommended Operating Conditions

Table 2117: Recommended Module recommended operating conditions

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 85 50 mm × 85 40 mm.   Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 5 8 mm.

• PCB thickness: 1.7 mm.65 mm.

• Highest part on PCB: approximately 3 mm. Please download the step model for exact numbers.

All dimensions are shown given in millimeters.

Revision History

Hardware Revision History

Table 2218: Hardware revision history table Module hardware revision history

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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Table 18: Document change history

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