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I/O signals connected to the SoCs I/O bank and B2B connector:

Table 2: General overview of FPGA's PL I/O signals connected to the FMC connector

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PCI Express Interface

The TEF1001 FPGA board is a PCI Express card designed to fit into systems with PCI Express x8 slots (PCIe 2.0 or higher) and is PCIe Gen. 2 capable. See next section for the overview of FPGA MGT lanes routed to the PCIe interface.

MGT Lanes

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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. The MGT lanes are connected to the FMC connector and to the PCIe x8 connector. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection connector and FPGA pins connection:

Table 3: FPGA to B2B connectors routed MGT lanes overview

Below are listed MGT banks reference clock sources:

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Table 4: MGT reference clock sources

JTAG Interface

JTAG access to the Xilinx Kintex UltraScale FPGA is available through B2B connector JM2.

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JTAG Signal

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B2B Connector Pin

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Table 5: JTAG interface signals

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Below are listed MGT banks reference clock sources:

Table 4: MGT reference clock sources

JTAG Interface

There are three JTAG interfaces available on the TEF1001 board:

Table 5: JTAG interface signals

System Controller CPLD I/O Pins

Special purpose pins are connected to the System Controller CPLD and have following default configuration:

Table 6: System Controller CPLD I/O pins

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Quad SPI interface is connected to the FPGA configuration bank 0.

Table 7: Quad SPI interface signals and connections

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On-module I²C interface is routed  from PL bank 65 I/O pins (PLL_SCL and PLL_SDA) to the I²C interface of Si5338 PLL quad clock generator U2, also two further pins of bank 65 can be used as external I²C interface of the modue:

Table 8: I²C slave device addresses

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DDR3 SD-RAM SODIMM Socket

By default TE0841 module has two K4A8G165WB-BIRC DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 2 GBytes of on-module RAM. Different memory sizes are available optionally.

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There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

 Table 9: Programmable quad PLL clock generator inputs and outputs, *PCB REV01 is not programmed

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The FPGA module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

Table 10: Reference clock signals

On-board LEDs

Table 11: On-board LEDs

Power and Power-On Sequence

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Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 12: Typical power consumption

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Power Rails

Table 13: Module power rails

Bank Voltages

Table 14: Module PL I/O bank voltages

Board to Board Connector

Include Page4 x 5 SoM LSHM B2B Connectors4 x 5 SoM LSHM B2B Connectors

Variants Currently In Production

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See also the current available variants on the Trenz Electronic shop page

Technical Specifications

Absolute Maximum Ratings

Table 16: Module absolute maximum ratings

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Recommended Operating Conditions

Table 17: Module recommended operating conditions

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Hardware Revision History

Table 18: Module hardware revision history

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Table 18: Document change history

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