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Pin Name	SC CPLD Direction	Function	Default Configuration
200MHZCLK_EN	out	control line	enables 200.0000MHz oscillator U1
BUTTON	in	user	Reset Button
CPLD_TDO	out	CPLD JTAG interface	-
CPLD_TDI	in
CPLD_TCK	in
CPLD_TMS	in
JTAG_EN	in
DDR3_SCL	in / out	I²C bus of DDR3 SODIMM socket	I²C connected to FPGA
DDR3_SDA	in / out	I²C bus of DDR3 SODIMM socket	I²C connected to FPGA
PLL_SCL	in / out	I²C bus of SI5338 quad clock PLL	I²C connected to FPGA
PLL_SDA	in / out	I²C bus of SI5338 quad clock PLL	I²C connected to FPGA
PCIE_RSTB	in	PCIe reset input	see current SC CPLD firmware
FEX_DIR / FEX0 ... FEX11	in / out	user GPIO	see current SC CPLD firmware
F1PWM	out	FPGA FAN control	see current SC CPLD firmware
F1SENSE	in	FPGA FAN control
FAN_FMC_EN	out	FMC FAN enable
FMC_PG_C2M	out	FMC signals and pins	see current SC CPLD firmware
FMC_PG_M2C	in
FMC_PRSNT_M2C_L	in
FMC_SCL	in / out	FMC I²C	I²C connected to FPGA
FMC_SDA	in / out	FMC I²C	I²C connected to FPGA
FMC_TCK		FMC JTAG	see current SC CPLD firmware
FMC_TDI
FMC_TDO
FMC_TMS
FMC_TRST
DONE	in	FPGA configuration signal	PL configuration completed
PROGRAM_B	out	FPGA configuration signal	PL configuration reset signal
LED1	out	LED status signal	see current CPLD firmware
FPGA_IIC_OE	in	I²C bus between FPGA and SC CPLD	I²C operation output enable
FPGA_IIC_SCL	in / out		I²C clock line
FPGA_IIC_SDA	in / out		I²C data line
EN_1V8	out	Power control	enable signal DCDC U20 '1V8'
PG_1V8	in		power good signal DCDC U20 '1V8'
EN_3V3FMC	out		enable signal DCDC U15 'EN_3V3FMC'
PG_3V3	in		power good signal U15 'EN_3V3FMC'
EN_FMC_VADJ	out		enable signal DCDC U7 'FMC_VADJ'
PG_FMC_VADJ	in		power good DCDC U7 'FMC_VADJ'
VID0_FMC_VADJ, VID1_FMC_VADJ, VID2_FMC_VADJ	out		DCDC U7 power selection pin
VID0_FMC_VADJ_CTRL, VID1_FMC_VADJ_CTRL, VID2_FMC_VADJ_CTRL	in		Power selection of FMC_VADJ, forwarded to DCDC U7
LTM_1V5_RUN	out		enable signals of DCDC U3, U4 (LTM4676) see current CPLD firmware
LTM_4V_RUN	out
LTM_SCL	in / out	DCDC U3, U4 (LTM4676) I²C	I²C connected to FPGA
LTM_SDA	in / out	DCDC U3, U4 (LTM4676) I²C	I²C connected to FPGA
LTM1_ALERT	in	DCDC U3, U4 (LTM4676) control	see current CPLD firmware
LTM2_ALERT	in
LTM_1V_IO0	in / out
LTM_1V_IO1	in / out
LTM_1V5_4V_IO0	in / out
LTM_1V5_4V_IO1	in / out

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Quad SPI Interface

Quad SPI Flash memory interface is connected to the FPGA bank 14, QSPI clock is provided by FPGA config bank 0.

Signal Name	QSPI Flash Memory U12 Pin	FPGA Pin
FLASH_QSPI_CS	C2	S, Pin 7	Bank 14, Pin C23RDWR_FCS_B_0, AH7
FLASH_QSPI_D0	D3	D00	DQ0, Pin 15	Bank 14, Pin B24D00_MOSI_0, AA7
FLASH_QSPI_D1	D2	D01	DQ1, Pin 8	Bank 14, Pin A25D01_DIN_0, Y7
FLASH_QSPI_D2	C4	D02	DQ2, Pin 9	Bank 14, Pin B22D02_0, U7
FLASH_QSPI_D3	D4	D03	DQ3, Pin 1	Bank 14, Pin A22D03_0, V7
FPGA_CFG_CCLK	B2	C, Pin 16	Bank CCLK_ 0, V11Pin C8

Table 7: Quad SPI interface signals and connections

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On-module I²C interface is routed from PL bank 65 14 I/O pins (PLLFPGA_IIC_SDA, FPGA_IIC_SCL and PLLFPGA_IIC_SDAOE) to the I²C interface of Si5338 PLL quad clock generator U2, also two further pins of bank 65 can be used as external I²C interface of the modue:

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'PLL_SCL', pin AB20

'PLL_SDA' pin AB19

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Si5338 U2, pin 12

Si5338 U2, pin 19

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SC CPLD U5 which works as I²C switch with the FPGA as I²C-Master. The I²C interfaces of the on-board peripherals are muxed to the FPGA I²C interface via SC CPLD U5. Also the FAN control of the 4-wire PWM FAN connector J4 can be controlled via I²C from FPGA. For detailed information, refer to the reference page of the SC CPLD firmware of this module, section I²C.

I²C Interface	Schematic net names	Connected to	I²C Address	Notes
PL bank 14 I/O	'FPGA_IIC_SDA', pin G25 'FPGA_IIC_SCL', pin G26 'FPGA_IIC_OE', pin F25	SC CPLD U5, pin 16 SC CPLD U5, pin 1 SC CPLD U5, pin 14	-	-
Si5338A, U13	'PLL_SDA', pin 19 'PLL_SCL', pin 12	SC CPLD U5, pin 8 SC CPLD U5, pin 2	0x70	-
LTM4676 U2, U3	'LTM_SDA', pin D6 'LTM_SCL', pin E6	SC CPLD U5, pin 66 SC CPLD U5, pin 67	U4: 1001111 U3: 1000000	-
DDR3 SODIMM, U2	'DDR3_SDA', pin 200 'DDR3_SCL', pin 202	SC CPLD U5, pin 42 SC CPLD U5, pin 43	module dependent	-
FMC Connector, J2	'FMC_SDA', pin C31 'FMC_SCL', pin C30	SC CPLD U5, pin 48 SC CPLD U5, pin 49	0x50	-

Table 8: I²C slave device addresses

FAN Connectors

The TEF1001 board offers two FAN connectors for cooling the FPGA device and on built-in FAN for the FMC modules.

Connector	Schematic net names	Connected to	Notes
4-Wire PWM FAN connector J4, 12V power supply	'F1SENSE', pin 3 'F1PWM', pin 4	SC CPLD U5, pin 99 SC CPLD U5, pin 98	FPGA cooling FAN can be controlled via I²C interface from FPGA, see current SC CPLD firmware
2-pin FAN connector J6, 5V power supply with TPS2051 Load Switch U25	'FAN_FMC_EN', U25 pin 4	SC CPLD U5, pin 78	FMC cooling FAN

Table 9: FAN connectors

On-board Peripherals

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System Controller CPLD

The System Controller CPLD (U5) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware,

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'B65_SCL', pin Y19

'B65_SDA', pin AA19

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B2B JM1, pin 95

B2B JM1, pin 93

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Table 8: I²C slave device addresses

On-board Peripherals

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<!-- Components on the Module, like Flash, PLL, PHY... -->

System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

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DDR3 SD-RAM SODIMM Socket

By default TE0841 module has two K4A8G165WB-BIRC DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 2 GBytes of on-module RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

 the SC CPLD.
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DDR3 SDRAM SODIMM Socket

The TEF1001 board supports additional DDR3 SODIMM via 204-pin socket U2. The DDR3 memory interface has a 64bit wide databus and is routed to the FPGA banks 32, 33 and 34.

The reference clock signal for the DDR3 interface is generated by the 200.0000MHz MEMS oscillator U1 and is applied to the FPGA bank 33.

There is also a I²C interface between the System Controller CPLD U5 and the DDR3 SODIMM memory socket U2.

Quad SPI Flash Memory

A 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron N25Q256A, U12) is provided for FPGA configuration file storage. After configuration process completes the remaining free memory can be used for application On-module QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q512A11G1240E with 512-Mbit (64 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. Maximum The maximum data rate depends on the selected bus width and clock frequency usedtransfer rate depends on the bus width and clock frequency. The memory can be accessed indirectly by the FPGA JTAG port (J9) by implementing the functional logic for this purpose inside the FPGA.

Note
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

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There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U2U13) to generate various reference clocks for the module.

Si5338A Pin	Signal Name / Description	Connected to	Direction	Note
IN1	-	not connected	Input	not used
IN2	-	GND	Input	not used
IN3	Reference input clock	U3, pin 3	Input	25.000000 MHz oscillator U14, Si8208AI
IN4	-	GND	Input	I²C slave device address LSB.
IN5	-	not connected	Input	not used
IN6	-	GND	Input	not used
CLK0A	CLK1CLK0_P	U1U6, R23G24	Output	FPGA bank 45, default 100MHz*-
CLK0B	CLK1CLK0_N	U1U6, P23F24	Output	FPGA bank 45, default 100MHz*-
CLK1A	MGTMGTCLK_CLK15338_NP	U1U6, V5G22	Output	FPGA MGT bank 225 reference clock, default 125MHz*-
CLK1B	MGTMGTCLK_CLK15338_PN	U1U6, V6F23	Output	FPGA MGT bank 225 reference clock, default 125MHz*-
CLK2A	MGTCLK1_CLK3_NP	U1U6, AB5 G22	Output	FPGA MGT bank 224 reference clock, default 156,25MHz*-
CLK2B	MGTCLK1_CLK3_PN	U1U6, AB6F23	Output	FPGA MGT bank 224 reference clock, default 156,25MHz*-
CLK3A	CLK0CLK2_P	U1U6, pin T24D23	Output	FPGA bank 45, default 156,25MHz*-
CLK3B	CLK0CLK2_N	U1U6, pin T25D24	Output	FPGA bank 45, default 156,25MHz*-

Table 910: Programmable quad PLL clock generator inputs and outputs, *PCB REV01 is not programmed

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Clock Source

Frequency

Signal Name

Clock Destination

Notes

U3, SiT8208AI

25.000000 MHz

CLK

Si5338A PLL U2, pin 3 (IN3)

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U11, DSC1123DL5

200.0000 MHz

CLK200M_P

FPGA bank 45, pin R25

Enable by FPGA bank 65, pin AF24

Signal: 'ENOSC'

CLK200M_N

FPGA bank 45, pin R26

Table 1011: Reference clock signals

On-board LEDs

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Parameter	Min	Max	Units	Reference Document
VIN supply voltage	11.4	12.6	V	12V nominal, ANSI/VITA 57.1 power specification for FMC connector
Supply voltage for HR I/O banks (VCCO)	1.140	3.465	V	Xilinx datasheet DS182
Supply voltage for HP I/O banks (VCCO)	1.140	1.890	V	Xilinx datasheet DS182
I/O input voltage for HR I/O banks	–0.500	VCCO + 0.20	V	Xilinx datasheet DS182
I/O input voltage for HP I/O banks	–0.500	VCCO + 0.20	V	Xilinx datasheet DS182
Differential input voltage	-0.2	2.625	V	Xilinx datasheet DS182
I/O input voltage for SC CPLD U5	-0.3	3.6	V	Lattice MachXO2 Family datasheet
Voltages on LTM4676 I²C pins (LTM_SCL, LTM_SDA), header J10	0	3.3V	V	LTM4676A datasheet
Industrial Module Operating Temperature Range	-40	85	°C	Xilinx datasheet DS182
Commercial Module Operating Temperature Range	0	85	°C	Xilinx DS182, Silicon Labs Si5338 datasheetdatasheets

Table 17: Module recommended operating conditions

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Note
Please check also Xilinx datasheet DS182 for complete list of absolute maximum and recommended operating ratings.

Physical Dimensions

Module Board size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: ca. 1.65 55 mm.Highest part on PCB: approximately 3 mm. Please download the step model for exact numbers.
The board meets the PCIe standard specifications for the dimensions

All dimensions are given in millimeters.

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Date	Revision	Notes	PCN	Documentation Link
2018-05-11	02	current available board revision	-	-
2015-12-09	01	First production release	PCN-20180524 TEF1001-01	TEF1001-01

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Trenz Electronic Documentation

Versions Compared

Old Version 18

New Version 19

Key

Quad SPI Interface

FAN Connectors

On-board Peripherals

System Controller CPLD

On-board Peripherals

System Controller CPLD

DDR3 SD-RAM SODIMM Socket

Quad SPI Flash Memory

DDR3 SDRAM SODIMM Socket

Quad SPI Flash Memory

On-board LEDs

Physical Dimensions