If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add a note, that this part is configurable
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
Figure template:
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Figure x: Text
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Example
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The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
<type>_<main section>_<name>
type: Figure, Table
main section:
"OV" for Overview
"SIP" for Signal Interfaces and Pins,
"OBP" for On board Peripherals,
"PWR" for Power and Power-On Sequence,
"B2B" for Board to Board Connector,
"TS" for Technical Specification
"VCP" for Variants Currently in Production
"RH" for Revision History
name: custom, some fix names, see below
Fix names:
"Figure_OV_BD" for Block Diagram
"Figure_OV_MC" for Main Components
"Table_OV_IDS" for Initial Delivery State
"Table_PWR_PC" for Power Consumption
"Figure_PWR_PD" for Power Distribution
"Figure_PWR_PS" for Power Sequence
"Figure_PWR_PM" for Power Monitoring
"Table_PWR_PR" for Power Rails
"Table_PWR_BV" for Bank Voltages
"Table_TS_AMR" for Absolute_Maximum_Ratings
"Table_TS_ROC" for Recommended_Operating_Conditions
"Figure_TS_PD" for Physical_Dimensions
"Table_VCP_SO" for TE_Shop_Overview
"Table_RH_HRH" for Hardware_Revision_History
"Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>
...
...
The Trenz Electronic TEC0850 board is a CompactPCI Serial card (3U form factor) integrating a Xilinx Zynq UltraScale+ MPSoC, one DDR4 SDRAM SODIMM socket with 64bit wide data bus, max. dual 512 MByte Flash memory for configuration and operation, 24 Gigabit transceivers on PL side and 4 on PS side, powerful switch-mode power supplies for all onboard voltages, USB2 and USB3 FIFO bridges and a large number of configurable I/Os available on the CompactPCI Serial backplane connectors.
Refer to http://trenz.org/tec0850-info for the current online version of this manual and other available documentation.
...
Zynq UltraScale+ MPSoC ZU15
Front side interface connectors
RJ-45 GbE Ethernet interface
Circular push/pull connector with 4x on-board 8bit DAC output
MicroSD Card connector
USB 2.0 and USB 3.0 to FIFO bridge connector
4x status LEDs
4 CompactPCI Serial connectors for backplane connection (3U form factor)
24 GTH lanes
4 PS GTR lanes
USB 2.0 interface
64 Zynq PL HP I/O's
8x PLL clock input
JTAG, I²C and 7 user I/O's to MAX10 FPGA
64bit DDR4 SODIMM (PS connected), 8 GByte maximum
Dual parallel QSPI Flash (bootable), 512 MByte maximum
26-pin header with 20 Zynq PL HD I/O's
3-pin header with 2 MAX10 FPGA I/O's
System Controller (Altera MAX10 FPGA SoC)
Power Sequencing
System management and control for MPSoC and onboard peripherals
Si5345 programmable 10 output PLL clock generator
Si53340 Quad clock buffer
2x 4bit DIP switches
1x user push button
Zynq MPSoC cooling FAN connector
On-board high-efficiency DC-DC converters
...
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Figure_OV_BD
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TEC0850-02 block diagram
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Main Components
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Notes :
Picture of the PCB (top and bottom side) with labels of important components
Add List below
...
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Figure_OV_MC
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TEC0850-02 main components
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GbE RJ-45 MagJack, J7
5-pin circular push/pull receptacle connector for DAC output, J15
Micro USB 2.0 B receptacle connector, J9
MicroSD Card socket, J11
USB 3.0 Type C connector, J10
LED light pipes J14 integrating LEDs D1 ... D4
4bit DIP-switch, S2
4bit DIP-switch, S1
FTDI FT2232 USB 2.0 to UART/JTAG bridge, U4
3-pin PicoBlade header, J8
MAX10 FPGA JTAG/UART 10-pin header, J13
Altera MAX10 System Controller FPGA, U18
4-Wire PWM fan connector, J17
26-pin IDC header for FPGA PL I/O's, J16
DDR4 SO-DIMM 260-pin socket, U3
Battery Holder CR1220, B1
256 Mbit (32 MByte) Micron Serial NOR Flash Memory N25Q256A, U24
256 Mbit (32 MByte) Micron Serial NOR Flash Memory N25Q256A, U25
DC-DC Converter LT8471IFE @+5VA/-5VA, U74
DC-DC Converter EM2130L02QI @VCCINT_0V85, U17
DC-DC Converter 171050601 @5V, U50
Xilinx Zynq Ultrascale+ MPSoC, U1
Si5345A 10-output I²C programmable PLL clock, U14
Main power fuse @2.5A/16V, F1
cPCI connector, J1
cPCI connector, J4
cPCI connector, J5
cPCI connector, J6
FTDI FT601Q USB 3.0 to FIFO bridge, U9
TI THS5641 8bit DAC ,U28
TI THS5641 8bit DAC ,U31
TI THS5641 8bit DAC ,U29
TI THS5641 8bit DAC ,U33
Marvell Alaska 88E1512 GbE PHY ,U20
...
Page properties
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true
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Comments
Notes :
For carrier or stand-alone boards use subsection for every connector type (add designator on a description, not on the subsection title), for example:
SD
USB
ETH
FMC
...
For modules which need carrier us only classes and refer to B2B connector if more than one is used, for example
JTAG
UART
I2C
MGT
...
CompactPCI Serial Backplane Connectors
The TEC0850 board is equipped with 3 CompactPCI CompactPCI Serial high-speed backplane connectors which provide serial high-speed interconnects with transmission rates up to 12 Gb/s to the Zynq MPSoCs MGT lanes. On the cPCI connectors are also available single-ended Zynq MPSoC PL HP I/O's, high-speed USB 2.0 interface and single-ended I/O's of the System Controller FPGA.
...
Following diagram gives an overview of the CompactPCI Serial backplane connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller FPGA U18:
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Figure_SIP_CompactPCI
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TEC0850-02 CompactPCI I/O and high-speed interfaces
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Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the cPCI connectors:
CompactPCI Serial connector J2 J3 is not fittedby default on the TEC0850 board by default, but is necessary if the second optional USB2 PHY U13 if fitted and its USB2 differential serial data interface is connected to the cPCI connector J2.
MGTHRXP3_229, F2 MGTHRXN3_229, F1 MGTHTXP3_229, F6 MGTHTXN3_229, F5
...
Anchor
CompactPCI Connector J6
CompactPCI Connector J6
CompactPCI Serial Connector J6
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Table_SIP_cPCI_J6_io
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cPCI J6 Interfaces
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Interfaces
I/O Signal Count
LVDS-pairs count
Connected to
VCCO bank Voltage
Notes
I/O
46
23
PL bank 66
PL_1.8V
-
18
9
PL bank 65
PL_1.8V
-
2
-
SC FPGA U18 Bank 1B
+3V_D
Signalname: 'DET_RIO', 'DET_BPR'
...
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Figure_SIP_usb3
title
TEC0850-02 USB3 to FIFO bridge
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The USB 3.0 to FIFO bridge FTDI FT601Q U9 is connected to the Zynq MPSoC's PL bank 64 and is accessible through USB-C connector J10:
...
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Figure_SIP_jtag_uart
title
JTAG/UART Interface
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The USB2 to FIFO bridge FTDI FT2232H U4 is connected to the SC FPGA U18 and is accessible through Micro-USB2 connector J9:
...
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Figure_SIP_microsd
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MicroSD Card interface
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TEC0850 SD IO
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There are some limitations to use SD card Interface in Linux.
...
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Figure_SIP_eth
title
Gigabit Ethernet Interface
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TEC0850 GbE
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DDR4 SODIMM Socket
On the TEC0850 board, there is a DDR4 memory interface U3 with a 64-bit data bus width available for SO-DIMM modules connected to the Zynq UltraScale+ DDRC hard memory controller.
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Figure_SIP_ddr4
title
DDR4 SDRAM SODIMM socket
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Following table gives an overview of the memory interface I/O signals of the DDR4 SDRAM SO-DIMM Socket U3:
...
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anchor
Figure_SIP_dac
title
4x 8bit DAC units
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TEC0850 DACs
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26-Pin IDC Header
There is a 26-pin IDC header (2x13, 1.27mm grid size) J16 available on the TEC0850 board which exposes the 20 FPGA HD I/O's of PL bank 47 to the user. The PL bank 47 has 3.3V VCCO bank voltage, on the header J16 there also the voltage levels 3.3V and 5V available. The I/O's can be accessed with a corresponding IDC connector.
Scroll Title
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Figure_SIP_idc_mpsoc_pl
title
Zynq MPSoC PL I/O's IDC pin-header
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10-Pin Header
On the TEC0850 there is a 10-pin SMT header (2x5, 2.54mm grid size) J13 present which provides access to the JTAG and UART interface of Altera MAX10 System Controller FPGA. The header J13 has a compatible pin assignment to the TEI0004 JTAG programmer for Altera FPGAs, the voltage levels 3.3V is on the header available as a reference I/O-voltage for JTAG and UART.
...
On the header J13, there is also a optional reference clock signal from PLL clock U14 available, which can be also if the necessary resistors and capacitors are fitted on board. The clock can also be used for the SC FPGA U18 and on the cPCI connector J1.
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Figure_SIP_10pin_jtag_uart
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10-pin JTAG/UART header
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TEC0850 header 13
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3-Pin PicoBlade Header
2 I/O's of the SC FPGA U18 are exposed to the on-board 3-Pin PicoBlade header J8 available to the user or for future use of upcoming versions of SC FPGA firmware.
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Figure_SIP_3pin_picoblade
title
3-pin PicoBlade header
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TEC0850 3-pin header J8
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Battery Holder
There is a CR1220 battery holder available to the supply the voltage for the Zynq MPSoC's Battery Power Domain (BBRAM and RTC). The battery voltage VBATT should be in the range of 2.2V to 5.5V, use the 3.0V CR1220 battery.
Scroll Title
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Figure_SIP_Battery_Holder
title
Backup-Battery Holder
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4-Wire PWM FAN Connectors
...
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Figure_SIP_fan
title
4-wire PWM FAN connector
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Onboard Peripherals
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Notes :
add a subsection for every component which is important for design, for example:
Following table shows onboard Silicon Labs I2C programmable Si5345A U17 10-output programmable PLL reference clock generator inputs and outputs:
...
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Figure_OBP_ft2232
title
TEC0850 on-board FTDI chips
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TEC0850 FT2232H
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FT2232H
The TEC0850 board is equipped with the FTDI FT2232H USB2 to JTAG/UART adapter controller connected to micro-USB2 connector J9 to provide JTAG and UART access to the Xilinx UltraScale+ Zynq SoC or Intel MAX10 (switchable over DIP) . There is also a 256-byte configuration EEPROM U6 wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools. Refer to the FTDI datasheet to get information about the capacity of the FT2232H chip.
...
Scroll Title
anchor
Figure_OBP_qspi
title
Quad-SPI Flash Memory
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TEC0850 QSPI Flash
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Table_OBP_QSPI_FLASH
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Quad-SPI Flash memory interface connections
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IC
Memory Density
MIO
Signal Schematic Name
Flash Memory Pin
QSPI Flash U24,
N25Q256A11E1240E
256 Mbit (32 MByte)
0
MIO0
B2
1
MIO1
D2
2
MIO2
C4
3
MIO3
D4
4
MIO4
D3
5
MIO5
C2
QSPI Flash U25,
N25Q256A11E1240
256 Mbit (32 MByte)
7
MIO7
C2
8
MIO8
D3
9
MIO9
D2
10
MIO10
C4
11
MIO11
D4
12
MIO12
B2
...
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Figure_OBP_eeprom
title
On-board configuration EEPROMs
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TEC0850 USB3 to FIFO
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The EEPROMs U63 and U64 are programmable via the onboard I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.
...
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Figure_OBP_usb2_phy
title
TEC0850 cPCI USB2 interface
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TEC0850 USB2 PHY
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Table_OBP_usb2_phy_io
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USB2 ULPI interface description
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USB2 PHY U11 Pin
Connected to
Notes
ULPI
PS bank MIO52 ... MIO63
Zynq Ultrascale+ USB0 MIO pins are connected to the PHY
REFCLK
-
52MHz from onboard oscillator U12
REFSEL[0..2]
-
All pins set to GND selects the external reference clock frequency (52.000000 MHz)
RESETB
Zynq MPSoC MIO16, pin AM16
Low active USB2 PHY Reset
DP, DM
cPCI connector J1
USB2 data lane
CPEN
-
External USB power switch active-high enable signal
VBUS
5V
Connected to onboard 5V voltage level via a series of resistors, see schematic
ID
3.3V
USB2 OTG A-Device (host)
optional USB2 PHY U13 Pin
Connected to
Notes
ULPI
PS bank MIO64 ... MIO75
Zynq Ultrascale+ USB1 MIO pins are connected to the PHY
REFCLK
-
52MHz from onboard oscillator U12
REFSEL[0..2]
-
All pins set to GND selects the external reference clock frequency (52.000000 MHz)
RESETB
Zynq MPSoC MIO17, pin AP16
Low active USB2 PHY Reset
DP, DM
optional cPCI connector J3
USB2 data lane
CPEN
-
External USB power switch active-high enable signal
VBUS
5V
Connected to onboard 5V voltage level via a series of resistors, see schematic
ID
3.3V
USB2 OTG A-Device (host)
...
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Figure_OBP_eth_phy
title
TEC0850 GbE interface with RJ-45 MegJack
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8bit DACs
The TEC0850 Board has 4 8-bit parallel Texas Instruments THS5641AIPW digital to analog converter (DAC) with up to 100 MSPS update rate connected to TI THS4631D operational amplifiers. See Schematic circuitry and TI THS5641 data sheet for proper operation of the on-board DAC units.
"S1-4 | S1-3 | S1-2 | S1-1 : Boot Mode":ON | ON | ON | ON : JTAG Boot Mode ON | ON | ON | OFF : Quad-SPI ON | ON | OFF | OFF : SD Card
of S2
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Dips
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BOOT Mode
1
2
3
4
Quad-SPI (32b
ON
ON
OFF
ON
SD1 (2.0)
ON
OFF
ON
OFF
JTAG
ON
ON
ON
ON
S2-2
MODE2
Zynq MPSOC PS Config Bank 503, pin T23
S2-3
MODE1
Zynq MPSOC PS Config Bank 503, pin R22
S2-4
MODE0
Zynq MPSOC PS Config Bank 503, pin T22
...
Power supply with a minimum current capability of 5A (60W@12V, CompactPCI Serial spec.) for system startup is recommended.
...
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Figure_PWR_PD
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Power Distribution
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Power supply
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Power-On Sequence
The TEC0850 board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the onboard DC-DC converters dedicated to the particular Power Domains and powering up the onboard voltages.
...
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Figure_PWR_PS
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Power-On Sequence Diagram
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TEC0850 Power-On Sequence Diagram
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Warning
To avoid any damage to the MPSoC module, check for stabilized onboard voltages in a steady state before powering up the MPSoC's I/O bank voltages VCCOx. All I/Os should be tri-stated during the power-on sequence.
...
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Figure_PWR_PM
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TEC0850 voltage Voltage monitor circuit
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TEC0850 Voltage Monitor Circuit
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Power Rails
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TEC0850 power rails description
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Connector / Pin
Voltage
Direction
Notes
J1, pin A1, D1, E1, G1, H1, J1, K1
VIN_12V
Input
Main power supply pins
J17, pin 2
12V
Output
4-wire PWM fan connector supply voltage
J13, pin 4
+3V_D
Output
JTAG/UART reference VCCIO voltage
B1, pin +
VBATT
Input
3.0V CR1220 battery
J16, pin 2
5V
Output
I/O header VCCIO
J16, pin 1
3.3V
Output
I/O header VCCIO
J9, pin 4
VBUS
Input
USB2 VBUS (5.0V nominal)
J10, pin A4, B9
VBUS30
Input
USB3 VBUS (5.0V nominal)
J11, pin 4
3.3V
Output
MicroSD Card VDD
J15, pin 2
DAC1_OUT
Output
DAC output
J15, pin 3
DAC2_OUT
Output
DAC output
J15, pin 4
DAC3_OUT
Output
DAC output
J15, pin 5
DAC4_OUT
Output
DAC output
...
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type
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false
boot mode bugfix
2018-10-26
v.103
John Hartfiel
change" Compact PCI" to "Compact PCI Serial"
v.102
Ali Naseri
small corrections
v.101
John Hartfiel
style changes
v.97
Ali Naseri
added information about the optional second USB2 PHY and cPCI connector J2 (not fitted by default)
