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The TEC0850 board is populated with the Zynq UltraScale+ XCZU15EG-1FFVB1156E MPSoC.
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I/O Interfaces
Main IO interfaces are shown on the image below.
| draw.io Diagram | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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PS MIO Configuration
| MIO | Interface |
|---|---|
| MIO 0...12 | QSPI Flash Memory |
| MIO 20...21 | I2C 1 |
| MIO 22...23 | UART 0 |
| MIO 26...37 | GEM 0 |
| MIO 46...51 | SD 1 |
| MIO 52...63 | USB 0 |
| MIO 64...75 | USB 1 |
| MIO 76...77 | MDIO 0 |
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| Tip |
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To force Linux driver not to use this features add following instructions to device tree file. &sdhci1 { no-1-8-v; |
USB
Board has 3 USB interfaces.
Front panel Micro-USB Interface
This interface provides access to UART and JTAG functions via FTDI FT2232 chip.
Front panel USB-C Interface
This interface connected to USB FIFO bridge chip FT601Q. 32-bit FIFO bridge provides a simple high-speed interface to Zynq UltraScale+ PL.
Backplane USB Interface
Zynq UltraScale+ USB controller connected to backplane connector J1C via USB PHY chip U11.
DACs
Board has 4 8-bit parallel Texas Instruments THS5641 DACs with up to 100 MSPS Update Rate.
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The TEC0850 board has 30 MGT lines routed to backplane connectors.
| Bank | Connector | Lanes |
|---|---|---|
| PL 128 | J4G and J4H | 4 |
| PL 129 | J5A and J5B | 4 |
| PL 130 | J5C and J5D | 4 |
| PL 230 | J4G and J4H | 4 |
| PL 229 | J5A and J5B | 4 |
| PL 228 | J5C and J5D | 4 |
| PS 505 | J1A | 4 |
MGT reference clocks are connected to banks 129, 229 and 505. Banks 128 and 130 should share clock from bank 129, banks 230 and 228 from bank 229.
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Overview
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