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Scroll Title |
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anchor | Table_x |
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title | Table x: FTDI Signals |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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FT601Q Signal | FPGA Pin |
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FIFO_CLK |
| ... |
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See FT600Q-FT601Q IC Datasheet for interface details.
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Scroll Title |
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anchor | Table_x |
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title | Table x: MGT Banks |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Bank | Connector | Lanes |
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PL 128 | J4G and J4H | 4 | PL 129 | J5A and J5B | 4 | PL 130 | J5C and J5D | 4 | PL 230 | J4G and J4H | 4 | PL 229 | J5A and J5B | 4 | PL 228 | J5C and J5D | 4 | PS 505 | J1A | 4 |
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MGT reference clocks are connected to banks 129, 229 and 505. Banks 128 and 130 should share clock from bank 129, banks 230 and 228 from bank 229.
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Scroll Title |
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anchor | Table_x |
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title | Table x: Default MIO Configuration |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO | Interface |
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MIO 0...12 | QSPI Flash Memory | MIO 20...21 | I2C 1 | MIO 22...23 | UART 0 | MIO 26...37 | GEM 0 | MIO 46...51 | SD 1 | MIO 52...63 | USB 0 | MIO 64...75 | USB 1 | MIO 76...77 | MDIO 0 |
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MAX10 System Controller
System controller chip is Intel MAX10 10M08SAU169C8G Chip with board control firmware.
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Scroll Title |
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anchor | Table_x |
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title | Table x: SI5345 I2C address |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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I2C address | Chip | Description |
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0x69 | U14 Si5345 | Clock generator and distributor |
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Oscillators
FTDIs
FT2232H
FT601Q-B-T
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Scroll Title |
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anchor | Table_x |
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title | Table x: EEPROMs I2C Addresses |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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I2C address | Chip | Description |
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0x50 | U63 24AA128T-I/ST | 128K Serial EEPROM | 0x53 | U64 24AA025E48T-I/OT | 2K Serial EEPROM with EUI-48™ or EUI-64™ Node Identity |
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USB PHY
Gigabit Ethernet PHY
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Scroll Title |
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anchor | Table_x |
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title | Table x: LEDs |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Switch | Description |
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1 | Boot Mode 0 | 2 | Boot Mode 1 | 3 | Boot Mode 2 | 4 | Boot Mode 3 |
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See Zynq UltraScale+ Device Technical Reference Manual page 236 for full boot modes description. Most common modes are
Scroll Title |
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anchor | Table_x |
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title | Table x: Recommended Boot Modes |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Boot Mode | SW1:4 | SW1:3 | SW1:2 | SW1:1 |
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JTAG Boot Mode | ON | ON | ON | ON | Quad-SPI | ON | ON | ON | OFF | SD Card | ON | ON | OFF | OFF |
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S2
Scroll Title |
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anchor | Table_x |
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title | Table x: S2 DIP Switch |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
---|
sortEnabled | false |
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cellHighlighting | true |
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|
Switch | Description |
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1 | SC JTAGEN | 2 | EEPROM WP (Write protect) | 3 | FPGA PUDC | 4 | SC Switch (Reserved for future use) |
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Buttons
LEDs
Scroll Title |
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anchor | Table_x |
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title | Table x: LEDs |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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LED | Signal | Chip | Pin | Description |
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Front panel LED 1 (Red) | LED_FP_1 | FPGA U1 | AF15 | PL User defined LED | Front panel LED 2 (Green) | LED_FP_2 | FPGA U1 | AG15 | PL User defined LED | Front panel LED 3 (Green) | LED_FP_3 | FPGA U1 | AE15 | PL User defined LED | Front panel LED 4 (Green) | LED_FP_4 | SC U18 | M4 | Power Good |
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Power and Power-On Sequence
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Scroll Title |
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anchor | Table_x |
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title | Table x: Typical power consumption. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
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Power Input | Typical Current |
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| TBD* |
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Power Distribution Dependencies
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Scroll Title |
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anchor | Table_x |
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title | Table x: Shop Overview |
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|
Scroll Table Layout |
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orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
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Revision History
Hardware Revision History
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