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| Scroll Title |
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| anchor | Table_x |
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| title | Table x: cPCI J5 clock signals: |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| PLL Clock U14 Output | Signal Schematic Name | cPCI Connector Pin J5 Pin | Notes |
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| OUT1 | | J5-A5
J5-B5 | Supplied reference clock signals supplied
by on-board
10-output
PLL clock generator U14 | | OUT2 | | J5-D5
J5-E5 | | OUT3 | | J5-G5
J5-H5 | | OUT4 | | J5-J5
J5-K5 | | OUT5 | | J5-B6
J5-C6 | | OUT6 | | J5-E6
J5-F6 | | OUT7 | | J5-H6
J5-I6 | | OUT8 | | J5-K6
J5-L6 |
|
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| Scroll Title |
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| anchor | Table_x |
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| title | Table x: Default MIO Configuration |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| PS MIO | Function | Connected to |
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| 0 | SPI0 | U24-B2, CLK |
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| 1 | SPI0 | U24-D2, DO/IO1
|
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| 2 | SPI0 | U24-C4, WP/IO2
|
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| 3 | SPI0 | U24-D4, HOLD/IO3 |
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| 4 | SPI0 | U24-D3, DI/IO0 |
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| 5 | SPI0 | U24-C2, CS |
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| 6 | - | Not connected |
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| 7 | SPI1 | U25-C2, CS |
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| 8 | SPI1 | U25-D3, DI/IO0 |
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| 9 | SPI1 | U25-D2, DO/IO1 |
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| 10 | SPI1 | U17-C4, WP/IO2 |
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| 11 | SPI1 | U25-D4, HOLD/IO3 |
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| 12 | SPI1 | U25-B2, CLK |
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| 13 ... 15 | - | not connected |
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| 16 | USB2 PHY Reset | USB2 PHY U11 |
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| 17 | - | not used |
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| 18 ... 19 | - | not connected |
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| 20 ...21 | PS MIO I²C | I²C peripherals |
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| 22 ... 25 | user MIO | SC FPGA U18, bank 2 |
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| 26 ... 38 | RGMII | GbE PHY U20 |
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| 39 ... 44 | - | not connected |
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| 45 ... 51 | SD IO | MicroSD Card socket J11 |
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| 52 ... 63 | USB2 ULPI | USB2 PHY U11 |
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| 64 ... 75 | - | not used |
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| 76 ... 77 | ETH MDC / MDIO | GbE PHY U20 |
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|
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| Scroll Title |
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| anchor | Table_x |
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| title | Table x: SI5345 I2C address |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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|
| Clock Source | Signal Schematic Name | Frequency | Clock Input Destination |
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| SiTime SiT8008BI oscillator, U22 | | 33.333333 MHz | Zynq MPSoC U1 PS Config Bank 503, pin U24 | | SiTime SiT8008AI oscillator, U12 | | 52.000000 MHz | USB2 transceiver PHY U11, pin 26 | | SiTime SiT8008AI oscillator, U16 | | 12.000000 MHz | FTDI FT2232H U4, pin 3 | | Kyocera CX3225SB30000, Y1 | - | 30.000 MHz | FTDI FT601Q U9, pin 21/22 | | CM-2012-2pad, Y2 | - | 32.768000 kHz | Zynq MPSoC U1 PS Config Bank 503, pin V21/V22 | | Kyocera CX3225SB26000, Y3 | | 54.000 MHz | 10-output PLL clock generator U14, pin 8/9 | | SiTime SiT8008BI oscillator, U21 | | 25.000000 MHz | Gigabit Ethernet PHY U20, pin 34 | | ASVTX-12-A oscillator, U75 | | 40.000 MHz | 10-output PLL clock generator U14, pin 63 |
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FTDIs
FT2232H
FT601Q
Quad-SPI Flash Memory
...
The TEC0850 board is equipped with 2 FTDI chips FT2232H (U4) and FT601Q (U9). Both chips are USB to Multipurpose UART/FIFO bridges which converts signals from USB2 or USB3 to a variety of standard serial and parallel interfaces.
FT2232H
The TEC0850 board is equipped with the FTDI FT2232H USB2 to JTAG/UART adapter controller connected to micro-USB2 connector J9 to provide JTAG and UART access to the Xilinx Zynq XC7Z010 SoC. There is also a 256-byte configuration EEPROM U6 wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
| Warning |
|---|
Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content. |
| Scroll Title |
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| anchor | Figure_11 |
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| title | Figure 11: CAN interface |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | true |
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| viewerToolbar | true |
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| |
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| fitWindow | false |
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| diagramName | TEC0850 FT2232H |
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| simpleViewer | false |
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| width | |
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| diagramWidth | 641 |
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| revision | 2 |
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|
|
|
Channel A of the FTDI IC is configured as JTAG interface (MPSSE) connected to the SC FPGA U18, the JTAG signals are forwarded to the JTAG interface of the Zynq MPSoC on PS config bank 503.
Channel B can be used as UART Interface routed to SC FPGA U18, 11 I/O's of Channel B are routed to are usable for example as GPIOs and other standard interfaces.
| Scroll Title |
|---|
| anchor | Table_x |
|---|
| title | Table x: SI5345 I2C address |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
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| cellHighlighting | true |
|---|
|
| FT2232H U3 Pin | Signal Schematic Name | Connected to | Notes |
|---|
| Pin 12, ADBUS0 | TCK | SC FPGA U18 bank 6, pin G9
| JTAG interface | | Pin 13, ADBUS1 | TDI | SC FPGA U18 bank 6, pin F10 | | Pin 14, ADBUS2 | TDO | SC FPGA U18 bank 6, pin E10 | | Pin 15, ADBUS3 | TMS | SC FPGA U18 bank 6, pin D9 | | Pin 32, BDBUS0 | BDBUS0 | SC FPGA U18 bank 6, pin B11 | user configurable | | Pin 33, BDBUS1 | BDBUS1 | SC FPGA U18 bank 6, pin A12 | | Pin 34, BDBUS2 | BDBUS2 | SC FPGA U18 bank 6, pin B12
| | Pin 35, BDBUS3 | BDBUS3 | SC FPGA U18 bank 6, pin C11 | | Pin 37, BDBUS4 | BDBUS4 | SC FPGA U18 bank 6, pin B13 | | Pin 38, BDBUS5 | BDBUS5 | SC FPGA U18 bank 6, pin C12 | | Pin 39, BDBUS6 | BDBUS6 | SC FPGA U18 bank 6, pin C13 | | Pin 40, BDBUS7 | BDBUS7 | SC FPGA U18 bank 6, pin D11 | | Pin 42, BCBUS0 | BCBUS0 | SC FPGA U18 bank 6, pin D12 | | Pin 46, BCBUS1 | BCBUS1 | SC FPGA U18 bank 6, pin E13 | | Pin 47, BCBUS2 | BCBUS2 | SC FPGA U18 bank 6, pin E12 | | Pin 48, BCBUS3 | BCBUS3 | SC FPGA U18 bank 6, pin F13 | | Pin 49, BCBUS4 | BCBUS4 | SC FPGA U18 bank 6, pin F12 |
|
FT601Q
| Scroll Title |
|---|
| anchor | Figure_11 |
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| title | Figure 11: CAN interface |
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|
|
Quad-SPI Flash Memory
Board has two N25Q512A11G1240E connected in a dual parallel mode.
| Scroll Title |
|---|
| anchor | Figure_11 |
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| title | Figure 11: CAN interface |
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|
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EEPROMs
The clock generator U14 is programmable via the on-board I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.
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