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title	Figure 1: TEC0850-02 block diagram

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draw.io Diagram

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anchor	Figure_23
title	Figure 23: TEC0850-02 Overview IO CompactPCI I/O and high-speed interfaces

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CompactPCI Connector J1

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title	Table x2: cPCI J1 interfaces

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Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
I/O	1	-	SC FPGA U18 Bank 6	+3V_D	control signals in cPCI pin assingment
I/O	6	-	SC FPGA U18 Bank 8	+3V_D	control signals in cPCI pin assingment
I²C	2	-	SC FPGA U18 Bank 1A	+3V_D	SC FPGA U18 I²C interface
JTAG	4	-	SC FPGA U18 Bank 1A	+3V_D	SC FPGA U18 JTAG interface
MGT	-	8 (4 x RX/TX)	Bank 502 PS GTR	-	4x PS GTR lanes
USB2	-	1 (RX/TX)	USB2 PHY U11	-	USB2 OTG A-Device (host)
Clock Input	-	1	Clock Driver U73	-	1x Reference clock input from PLL clock U14

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title	Table x3: cPCI J1 MGT lanes

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MGT Lane	Bank	Type	Signal Schematic Name	cPCI Connector Pin	FPGA Pin
0	505	GTR	PE1_RX0_P PE1_RX0_N PE1_TX0_P PE1_TX0_N	J1-D5 J1-E5 J1-A5 J1-B5	PS_MGTRRXP0_505, AB29 PS_MGTRRXN0_505, AB30 PS_MGTRTXP0_505, AB33 PS_MGTRTXN0_505, AB34
1	505	GTR	PE1_RX1_P PE1_RX1_N PE1_TX1_P PE1_TX1_N	J1-J5 J1-K5 J1-G5 J1-H5	PS_MGTRRXP1_505, Y29 PS_MGTRRXN1_505, Y30 PS_MGTRTXP1_505, AA31 PS_MGTRTXN1_505, AA32
2	505	GTR	PE1_RX2_P PE1_RX2_N PE1_TX2_P PE1_TX2_N	J1-E6 J1-F6 J1-B6 J1-C6	PS_MGTRRXP2_505, W31 PS_MGTRRXN2_505, W32 PS_MGTRTXP2_505, Y33 PS_MGTRTXN2_505, Y34
3	505	GTR	PE1_RX3_P PE1_RX3_N PE1_TX3_P PE1_TX3_N	J1-K6 J1-L6 J1-H6 J1-I6	PS_MGTRRXP3_505, V29 PS_MGTRRXN3_505, V30 PS_MGTRTXP3_505, V33 PS_MGTRTXN3_505, V34

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title	Table x4: cPCI J1 clock signals

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Clock Signal Schematic Name

cPCI Connector Pin

Header J13 Pin

SC FPGA U18 Pin

Notes

SATA_SL
SATA_SCL

J1-K3
J1-J3

J13-5
J13-1

Bank 1B, Pin G1
Bank 1B, Pin G2

Supplied by 10-output PLL clock U14,

cPCI connector J1 clock signal from PLL U14 is
also shared with SC FPGA and header J13

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title	Table x5: cPCI J1 VCC/VCCIO

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Available VCC/VCCIO	cPCI Connector Pin	Source	Notes
VIN_12V	J1-A1 J1-D1 J1-E1 J1-G1 J1-H1 J1-J1 J1-K1	cPCI backplane	min. cur.: 6.65A

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CompactPCI Connector J4

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title	Table x6: cPCI J4 MGT lanes

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MGT Lane	Bank	Type	Signal Schematic Name	cPCI Connector Pin	FPGA Pin
0	128	GTH	PE3_RX0_P PE3_RX0_N PE3_TX0_P PE3_TX0_N	J4-D1 J4-E1 J4-A1 J4-B1	MGTHRXP0_128, T33 MGTHRXN0_128, T34 MGTHTXP0_128, T29 MGTHTXN0_128, T30
1	128	GTH	PE3_RX1_P PE3_RX1_N PE3_TX1_P PE3_TX1_N	J4-J1 J4-K1 J4-G1 J4-H1	MGTHRXP1_128, P33 MGTHRXN1_128, P34 MGTHTXP1_128, R31 MGTHTXN1_128, R32
2	128	GTH	PE3_RX2_P PE3_RX2_N PE3_TX2_P PE3_TX2_N	J4-E2 J4-F2 J4-B2 J4-C2	MGTHRXP2_128, N31 MGTHRXN2_128, N32 MGTHTXP2_128, P29 MGTHTXN2_128, P30
3	128	GTH	PE3_RX3_P PE3_RX3_N PE3_TX3_P PE3_TX3_N	J4-K2 J4-L2 J4-H2 J4-I2	MGTHRXP3_128, M33 MGTHRXN3_128, M34 MGTHTXP3_128, M29 MGTHTXN3_128, M30
0	129	GTH	PE4_RX0_P PE4_RX0_N PE4_TX0_P PE4_TX0_N	J4-D3 J4-E3 J4-A3 J4-B3	MGTHRXP0_129, L31 MGTHRXN0_129, L32 MGTHTXP0_129, K29 MGTHTXN0_129, K30
1	129	GTH	PE4_RX1_P PE4_RX1_N PE4_TX1_P PE4_TX1_N	J4-J3 J4-K3 J4-G3 J4-H3	MGTHRXP1_129, K33 MGTHRXN1_129, K34 MGTHTXP1_129, J31 MGTHTXN1_129, J32
2	129	GTH	PE4_RX2_P PE4_RX2_N PE4_TX2_P PE4_TX2_N	J4-E4 J4-F4 J4-B4 J4-C4	MGTHRXP2_129, H33 MGTHRXN2_129, H34 MGTHTXP2_129, H29 MGTHTXN2_129, H30
3	129	GTH	PE4_RX3_P PE4_RX3_N PE4_TX3_P PE4_TX3_N	J4-K4 J4-L4 J4-H4 J4-I4	MGTHRXP3_129, F33 MGTHRXN3_129, F34 MGTHTXP3_129, G31 MGTHTXN3_129, G32
0	130	GTH	PE5_RX0_P PE5_RX0_N PE5_TX0_P PE5_TX0_N	J4-D5 J4-E5 J4-A5 J4-B5	MGTHRXP3_130, B33 MGTHRXN3_130, B34 MGTHTXP3_130, A31 MGTHTXN3_130, A32
1	130	GTH	PE5_RX1_P PE5_RX1_N PE5_TX1_P PE5_TX1_N	J4-J5 J4-K5 J4-G5 J4-H5	MGTHRXP2_130, C31 MGTHRXN2_130, C32 MGTHTXP2_130, B29 MGTHTXN2_130, B30
2	130	GTH	PE5_RX2_P PE5_RX2_N PE5_TX2_P PE5_TX2_N	J4-E6 J4-F6 J4-B6 J4-C6	MGTHRXP1_130, D33 MGTHRXN1_130, D34 MGTHTXP1_130, D29 MGTHTXN1_130, D30
3	130	GTH	PE5_RX3_P PE5_RX3_N PE5_TX3_P PE5_TX3_N	J4-K6 J4-L6 J4-H6 J4-I6	MGTHRXP0_130, E31 MGTHRXN0_130, E32 MGTHTXP0_130, F29 MGTHTXN0_130, F30
0	230	GTH	PE6_RX0_P PE6_RX0_N PE6_TX0_P PE6_TX0_N	J4-D7 J4-E7 J4-A7 J4-B7	MGTHRXP3_230, A4 MGTHRXN3_230, A3 MGTHTXP3_230, A8 MGTHTXN3_230, A7
1	230	GTH	PE6_RX1_P PE6_RX1_N PE6_TX1_P PE6_TX1_N	J4-J7 J4-K7 J4-G7 J4-H7	MGTHRXP2_230, B2 MGTHRXN2_230, B1 MGTHTXP2_230, B6 MGTHTXN2_230, B5
2	230	GTH	PE6_RX2_P PE6_RX2_N PE6_TX2_P PE6_TX2_N	J4-E8 J4-F8 J4-B8 J4-C8	MGTHRXP1_230, C4 MGTHRXN1_230, C3 MGTHTXP1_230, D6 MGTHTXN1_230, D5
3	230	GTH	PE6_RX3_P PE6_RX3_N PE6_TX3_P PE6_TX3_N	J4-K8 J4-L8 J4-H8 J4-I8	MGTHRXP0_230, D2 MGTHRXN0_230, D1 MGTHTXP0_230, E4 MGTHTXN0_230, E3

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CompactPCI Connector J5

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title	Table x7: cPCI J5 MGT lanes

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MGT Lane	Bank	Type	Signal Schematic Name	cPCI Connector Pin	FPGA Pin
0	228	GTH	PE8_RX0_P PE8_RX0_N PE8_TX0_P PE8_TX0_N	J5-D3 J5-E3 J5-A3 J5-B3	MGTHRXP0_228, T2 MGTHRXN0_228, T1 MGTHTXP0_228, R4 MGTHTXN0_228, R3
1	228	GTH	PE8_RX1_P PE8_RX1_N PE8_TX1_P PE8_TX1_N	J5-J3 J5-K3 J5-G3 J5-H3	MGTHRXP1_228, P2 MGTHRXN1_228, P1 MGTHTXP1_228, P6 MGTHTXN1_228, P5
2	228	GTH	PE8_RX2_P PE8_RX2_N PE8_TX2_P PE8_TX2_N	J5-E4 J5-F4 J5-B4 J5-C4	MGTHRXP2_228, M2 MGTHRXN2_228, M1 MGTHTXP2_228, N4 MGTHTXN2_228, N3
3	228	GTH	PE8_RX3_P PE8_RX3_N PE8_TX3_P PE8_TX3_N	J5-K4 J5-L4 J5-H4 J5-I4	MGTHRXP3_228, L4 MGTHRXN3_228, L3 MGTHTXP3_228, M6 MGTHTXN3_228, M5
0	229	GTH	PE7_RX0_P PE7_RX0_N PE7_TX0_P PE7_TX0_N	J5-D1 J5-E1 J5-A1 J5-B1	MGTHRXP0_229, K2 MGTHRXN0_229, K1 MGTHTXP0_229, K6 MGTHTXN0_229, K5
1	229	GTH	PE7_RX1_P PE7_RX1_N PE7_TX1_P PE7_TX1_N	J5-J1 J5-K1 J5-G1 J5-H1	MGTHRXP1_229, J4 MGTHRXN1_229, J3 MGTHTXP1_229, H6 MGTHTXN1_229, H5
2	229	GTH	PE7_RX2_P PE7_RX2_N PE7_TX2_P PE7_TX2_N	J5-E2 J5-F2 J5-B2 J5-C2	MGTHRXP2_229, H2 MGTHRXN2_229, H1 MGTHTXP2_229, G4 MGTHTXN2_229, G3
3	229	GTH	PE7_RX3_P PE7_RX3_N PE7_TX3_P PE7_TX3_N	J5-K2 J5-L2 J5-H2 J5-I2	MGTHRXP3_229, F2 MGTHRXN3_229, F1 MGTHTXP3_229, F6 MGTHTXN3_229, F5

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title	Table x8: cPCI J5 clock signals:

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PLL Clock U14 Output	Signal Schematic Name	cPCI Connector J5 Pin	Notes
OUT1	PE1_CLK_P PE1_CLK_N	J5-A5 J5-B5	reference clock signals supplied by on-board 10-output PLL clock generator U14
OUT2	PE2_CLK_P PE2_CLK_N	J5-D5 J5-E5
OUT3	PE3_CLK_P PE3_CLK_N	J5-G5 J5-H5
OUT4	PE4_CLK_P PE4_CLK_N	J5-J5 J5-K5
OUT5	PE5_CLK_P PE5_CLK_N	J5-B6 J5-C6
OUT6	PE6_CLK_P PE6_CLK_N	J5-E6 J5-F6
OUT7	PE7_CLK_P PE7_CLK_N	J5-H6 J5-I6
OUT8	PE8_CLK_P PE8_CLK_N	J5-K6 J5-L6

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CompactPCI Connector J6

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title	Table x9: cPCI J6 Interfaces

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Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
I/O	46	23	PL bank 66	PL_1.8V	-
	18	9	PL bank 65	PL_1.8V	-
	2	-	SC FPGA U18 Bank 1B	+3V_D	Signalname: 'DET_RIO', 'DET_BPR'

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title	Figure 24: TEC0850-02 Overview IO interfacesUSB3 to FIFO bridge

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The USB3 to FIFO bridge FTDI FT601Q U9 is connected to the Zynq MPSoC's PL bank 64 and is accessible through USB-C connector J10:

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Interface	Signal Schematic Names	Connected to	Notes
USB3 data lane	SSRX_P SSRX_N SSTXX_P SSTXX_N	USB C Connector J10	-
USB2 data lane	SS_D_P SS_D_N	USB C Connector J10	-
Control Lines	FTDI_RESET_N WAKEUP_N SIWU_N TXE_N RXF_N WR_N RD_N OE_N BE_0 BE_1 BE_2 BE_3 FIFO_CLK	PL bank 64	-
Parallel GPIO's	DATA0 . . DATA31	PL bank 64	32bit FIFO register

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title	Figure 35: JTAG/UART Interface

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The USB2 to FIFO bridge FTDI FT2232H U4 is connected to the SC FPGA U18 and is accessible through Micro-USB2 connector J9:

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title	Table x11: Micro-USB2 connector J9

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Interface	Signal Schematic Names	Connected to	Notes
USB2 data lane	USB_P USB_N	Micro-USB2 connector J9	-
Control Lines	FTDI_RST	SC FPGA U18, bank 6	-
Parallel GPIO's	ADBUS0 ADBUS1 ADBUS2 ADBUS3 BDBUS0 BDBUS1 BDBUS2 BDBUS3 BDBUS4 BDBUS5 BDBUS6 BDBUS7 BCBUS0 BCBUS1 BCBUS2 BCBUS3 BCBUS4	SC FPGA U18, bank 6	-

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Trenz Electronic Documentation

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