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anchor	Figure_38
title	Figure 3: JTAG/UART Interface8: DDR4 SDRAM SODIMM socket

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Following table gives an overview about the memory interface I/O signals of the DDR4 SDRAM SO-DIMM Socket U3:

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anchor	Table_x12
title	Table x12: DDR4 SDRAM SO-DIMM Socket socket U3

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DDR4 SDRAM I/O Signal	Signal Schematic Name	Connected to	Notes
Address inputs	DDR4-A0 ... DDR4-A16	PS DDR Bank 504	-
Bank address inputs	DDR4-BA0 / DDR4-BA1		-
Bank group inputs	DDR4-BG0 / DDR4-BG1		-
Differential clocks	DDR4-CLK0_P DDR4-CLK0_N DDR4-CLK1_P DDR4-CLK1_N		2 x DDR4 clock
Data input/output	DQ0 ... DQ63		-
Check bit input/output	CB0 ... CB7		-
Data strobe (differential)	DDR4-DQS0_P DDR4-DQS0_N ... DDR4-DQS8_P DDR4-DQS8_N		-
Data mask and data bus inversion	DDR4-DM0 ... DDR4-DM8		-
Serial address inputs	DDR4-SA0 ... DDR4-SA2		address range configuration on I²C bus
Control Signals	DDR4-CS_N0 / DDR4-CS_N1		chip selest signal
	DDR4-ODT0 / DDR4-ODT1		On-die termination enable
	DDR4-RESET		nRESET
	DDR4-PAR		Command and address parity input
	DDR4-CKE0 / DDR4-CKE1		Clock enable
	DDR4-ALERT		CRC error flag
	DDR4-ACT		Activation command input
	DDR4-EVENT		Temperature event
I²C	DDR4-SCL DDR4-SDA	not connected	-

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anchor	Figure_119
title	Figure 11: CAN interface9: 4x 8bit DAC units

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anchor	Figure_1110
title	Figure 11: CAN interface10: Zynq MPSoC PL I/O's IDC pin-header

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anchor	Figure_11
title	Figure 11: CAN interface10-pin JTAG/UART header

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3-Pin PicoBlade

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Header

2 I/O's of the SC FPGA U18 are exposed to the on-board 3-Pin PicoBlade header J8 available to the user or for future use of upcoming versions of SC FPGA firmware.

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title	Figure 11: CAN interface12: 3-pin PicoBlade header

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anchor	Figure_1113
title	Figure 11: CAN interface13: Backup-Battery Holder

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anchor	Figure_1314
title	Figure 1314: 4-wire PWM FAN connectors

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Trenz Electronic Documentation

Versions Compared

Old Version 66

New Version 67

Key

3-Pin PicoBlade

Header