...
| Scroll Title |
|---|
| anchor | Figure_10 |
|---|
| title | Figure 10: Zynq MPSoC PL I/O's IDC pin-header |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | false |
|---|
| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
|---|
| diagramDisplayName | |
|---|
| lbox | true |
|---|
| revision | 23 |
|---|
| diagramName | TEC0850 header J16 |
|---|
| simpleViewer | false |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| diagramWidth | 346641 |
|---|
|
|
|
On the TEC0850 there is a 10-pin SMT header (2x5, 2.54mm grid size) J13 present which provides access to the JTAG and UART interface of Altera MAX10 System Controller FPGA. The header J13 has a compatible pin assignment to the TEI0004 JTAG programmer for Altera FPGAs, the voltage levels 3.3V is on the header available as reference I/O-voltage for JTAG and UART.
...
| Scroll Title |
|---|
| anchor | Figure_14 |
|---|
| title | Figure 14: 4-wire PWM FAN connectorsconnector |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | false |
|---|
| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
|---|
| diagramDisplayName | |
|---|
| lbox | true |
|---|
| revision | 2 |
|---|
| diagramName | TEC0850 4-Wire PWM Connector |
|---|
| simpleViewer | false |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| diagramWidth | 641 |
|---|
|
|
| Scroll Only |
|---|
|
|
...
The PS MIO pins are routed to the on-board peripherals as follows:
| Scroll Title |
|---|
| anchor | Table_x13 |
|---|
| title | Table x13: Default MIO Configuration |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| PS MIO | Function | Connected to |
|---|
| 0 | SPI0 | U24-B2, CLK |
|---|
| 1 | SPI0 | U24-D2, DO/IO1
|
|---|
| 2 | SPI0 | U24-C4, WP/IO2
|
|---|
| 3 | SPI0 | U24-D4, HOLD/IO3 |
|---|
| 4 | SPI0 | U24-D3, DI/IO0 |
|---|
| 5 | SPI0 | U24-C2, CS |
|---|
| 6 | - | Not connected |
|---|
| 7 | SPI1 | U25-C2, CS |
|---|
| 8 | SPI1 | U25-D3, DI/IO0 |
|---|
| 9 | SPI1 | U25-D2, DO/IO1 |
|---|
| 10 | SPI1 | U17-C4, WP/IO2 |
|---|
| 11 | SPI1 | U25-D4, HOLD/IO3 |
|---|
| 12 | SPI1 | U25-B2, CLK |
|---|
| 13 ... 15 | - | not connected |
|---|
| 16 | USB2 PHY Reset | USB2 PHY U11 |
|---|
| 17 | - | not used |
|---|
| 18 ... 19 | - | not connected |
|---|
| 20 ...21 | PS MIO I²C | I²C peripherals |
|---|
| 22 ... 25 | user MIO | SC FPGA U18, bank 2 |
|---|
| 26 ... 38 | RGMII | GbE PHY U20 |
|---|
| 39 ... 44 | - | not connected |
|---|
| 45 ... 51 | SD IO | MicroSD Card socket J11 |
|---|
| 52 ... 63 | USB2 ULPI | USB2 PHY U11 |
|---|
| 64 ... 75 | - | not used |
|---|
| 76 ... 77 | ETH MDC / MDIO | GbE PHY U20 |
|---|
|
...