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titleTable 4: cPCI J1 clock signals

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Clock Signal Schematic NamecPCI Connector PinHeader J13 PinSC FPGA U18 PinNotes
  • SATA_SL
  • SATA_SCL

J1-K3
J1-J3

J13-5
J13-1

Bank 1B, Pin G1
Bank 1B, Pin G2

Supplied by 10-output PLL clock U14,

cPCI connector J1 clock signal from PLL U14 is
also shared with SC FPGA and header J13



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titleTable 5: cPCI J1 VCC/VCCIO

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Available VCC/VCCIOcPCI Connector PinSourceNotes
VIN_12V

J1-A1
J1-D1
J1-E1
J1-G1
J1-H1
J1-J1
J1-K1

cPCI backplane

min. cur.: 6.65A

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