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title	Table 4: cPCI J1 clock signals

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Clock Signal Schematic Name

cPCI Connector Pin

Header J13 Pin

SC FPGA U18 Pin

Notes

SATA_SL
SATA_SCL

J1-K3
J1-J3

J13-5
J13-1

Bank 1B, Pin G1
Bank 1B, Pin G2

Supplied by 10-output PLL clock U14,

cPCI connector J1 clock signal from PLL U14 is
also shared with SC FPGA and header J13

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title	Table 5: cPCI J1 VCC/VCCIO

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Available VCC/VCCIO	cPCI Connector Pin	Source	Notes
VIN_12V	J1-A1 J1-D1 J1-E1 J1-G1 J1-H1 J1-J1 J1-K1	cPCI backplane	min. cur.: 6.65A

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title	Table 8: cPCI J5 clock signals:

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PLL Clock U14 Output	Signal Schematic Name	cPCI Connector J5 Pin	Notes
OUT1	PE1_CLK_P PE1_CLK_N	J5-A5 J5-B5	reference clock signals supplied by on-board 10-output PLL clock generator U14
OUT2	PE2_CLK_P PE2_CLK_N	J5-D5 J5-E5
OUT3	PE3_CLK_P PE3_CLK_N	J5-G5 J5-H5
OUT4	PE4_CLK_P PE4_CLK_N	J5-J5 J5-K5
OUT5	PE5_CLK_P PE5_CLK_N	J5-B6 J5-C6
OUT6	PE6_CLK_P PE6_CLK_N	J5-E6 J5-F6
OUT7	PE7_CLK_P PE7_CLK_N	J5-H6 J5-I6
OUT8	PE8_CLK_P PE8_CLK_N	J5-K6 J5-L6

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Following table shows on-board Silicon Labs I²C programmable Si5345A U17 10-output programmable PLL reference clock generator inputs and outputs:

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title	Table x14: SI5345 I2C addressClock Outputs

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Si5345A U14 Pin	Signal Schematic Name	Connected to	Clock Direction	Note
IN0	IN0_P	40.000 MHz Oscillator U75	Input	external reference clock input
IN0	IN0_N	GND	Input	external reference clock input
IN1	-	not connected	Input	not used
IN1	-	not connected	Input	not used
IN2	-	not connected	Input	not used
IN2	-	not connected	Input	not used
IN3	-	not connected	Input	not used
IN3	-	not connected	Input	not used
OUT0	CLK0_P	Quad clock buffer Si53340 U16	Output	reference clock input to Quad clock buffer
OUT0	CLK0_N	Quad clock buffer Si53340 U16	Output	reference clock input to Quad clock buffer
OUT1	PE1_CLK_N	cPCI J5, pin B5	Output	reference clock output to cPCI connector J5
OUT1	PE1_CLK_P	cPCI J5, pin A5	Output
OUT2	PE5_CLK_N	cPCI J5, pin C6	Output
OUT2	PE5_CLK_P	cPCI J5, pin B6	Output
OUT3	PE2_CLK_N	cPCI J5, pin E5	Output
OUT3	PE2_CLK_P	cPCI J5, pin D5	Output
OUT4	PE3_CLK_N	cPCI J5, pin H5	Output
OUT4	PE3_CLK_P	cPCI J5, pin G5	Output
OUT5	PE4_CLK_N	cPCI J5, pin K5	Output
OUT5	PE4_CLK_P	cPCI J5, pin J5	Output
OUT6	PE6_CLK_N	cPCI J5, pin F6	Output
OUT6	PE6_CLK_P	cPCI J5, pin E6	Output
OUT7	PE8_CLK_N	cPCI J5, pin L6	Output
OUT7	PE8_CLK_P	cPCI J5, pin K6	Output
OUT8	PE7_CLK_N	cPCI J5, pin I6	Output
OUT8	PE7_CLK_P	cPCI J5, pin H6	Output
OUT9	CLK9_P	Clock Driver LTC6975 U73	Output	reference clock input to dual clock driver
OUT9	CLK9_N	Clock Driver LTC6975 U73	Output	reference clock input to dual clock driver
XA/XB	XAXB_P	54.000 MHz quartz oscillator Y3	Input	Differential quartz oscillator clock input
XA/XB	XAXB_N	54.000 MHz quartz oscillator Y3	Input	Differential quartz oscillator clock input
SCLK, SDA/SDIO	I2C_SCL I2C_SDA	MIO20 MIO21	BiDir	I²C address 0x69

The clock outputs OUT1 and OUT9 are distributed via clock buffer U16 and clock driver U14 to several PL and MGT banks:

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title	Table x: SI5345 I2C address15: Clock driver and buffer outputs

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Si53340 U16 Pin	Signal Schematic Name	Connected to	Clock Direction	Note
Q0	CLK1_P CLK1_N	U1, pin G8 U1, pin G7	Output	GTH bank 229 reference clock input
Q1	CLK2_P CLK2_N	U1, pin Y8 U1, pin Y7	Output	PL HP bank 66 reference clock input
Q2	CLK3_P CLK3_N	U1, pin U27 U1, pin U28	Output	PS GTR Bank 505 reference clock input
Q3	CLK4_P CLK4_N	U1, pin L27 U1, pin L28	Output	GTH bank 129 reference clock input
LTC6957 U14 Pin
OUT1	CK_PLL_P CK_PLL_N	U1, pin AG5 U1, pin AG4	Output	PL HP bank 65 reference clock input
OUT2	CK_P CK_N	Signal 'SATA_SL' Signal 'SATA_SCL'	Output	reference clock input cPCI connector J1, header J13 and SC FPGA U18

The clock generator U14 is programmable via the on-board I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.

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title	Table x16: SI5345 I2C address

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I2C address	Chip	Description
0x69	U14 Si5345	Clock generator and distributor

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The TEC0850 board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:

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title	Table x: SI5345 I2C address17: TEC0850 on-board oscillators

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Clock Source	Signal Schematic Name	Frequency	Clock Input Destination
SiTime SiT8008BI oscillator, U22	PS_CLK	33.333333 MHz	Zynq MPSoC U1 PS Config Bank 503, pin U24
SiTime SiT8008AI oscillator, U12	USB0_CLK	52.000000 MHz	USB2 transceiver PHY U11, pin 26
SiTime SiT8008AI oscillator, U16	OSCI	12.000000 MHz	FTDI FT2232H U4, pin 3
Kyocera CX3225SB30000, Y1	-	30.000 MHz	FTDI FT601Q U9, pin 21/22
CM-2012-2pad, Y2	-	32.768000 kHz	Zynq MPSoC U1 PS Config Bank 503, pin V21/V22
Kyocera CX3225SB26000, Y3	XAXB_P XAXB_N	54.000 MHz	10-output PLL clock generator U14, pin 8/9
SiTime SiT8008BI oscillator, U21	ETH_CLKIN	25.000000 MHz	Gigabit Ethernet PHY U20, pin 34
ASVTX-12-A oscillator, U75	IN0_P	40.000 MHz	10-output PLL clock generator U14, pin 63

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Channel B can be used as UART Interface routed to SC FPGA U18, 11 I/O's of Channel B are routed to are usable for example as GPIOs and other standard interfaces.

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title	Table x: SI5345 I2C address18: FT2232H interface connections

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FT2232H U3 Pin	Signal Schematic Name	Connected to	Notes
Pin 12, ADBUS0	ADBUS0	SC FPGA U18 bank 6, pin G9	JTAG interface
Pin 13, ADBUS1	ADBUS1	SC FPGA U18 bank 6, pin F10
Pin 14, ADBUS2	ADBUS2	SC FPGA U18 bank 6, pin E10
Pin 15, ADBUS3	ADBUS3	SC FPGA U18 bank 6, pin D9
Pin 32, BDBUS0	BDBUS0	SC FPGA U18 bank 6, pin B11	UART and user configurable GPIO's
Pin 33, BDBUS1	BDBUS1	SC FPGA U18 bank 6, pin A12
Pin 34, BDBUS2	BDBUS2	SC FPGA U18 bank 6, pin B12
Pin 35, BDBUS3	BDBUS3	SC FPGA U18 bank 6, pin C11
Pin 37, BDBUS4	BDBUS4	SC FPGA U18 bank 6, pin B13
Pin 38, BDBUS5	BDBUS5	SC FPGA U18 bank 6, pin C12
Pin 39, BDBUS6	BDBUS6	SC FPGA U18 bank 6, pin C13
Pin 40, BDBUS7	BDBUS7	SC FPGA U18 bank 6, pin D11
Pin 42, BCBUS0	BCBUS0	SC FPGA U18 bank 6, pin D12
Pin 46, BCBUS1	BCBUS1	SC FPGA U18 bank 6, pin E13
Pin 47, BCBUS2	BCBUS2	SC FPGA U18 bank 6, pin E12
Pin 48, BCBUS3	BCBUS3	SC FPGA U18 bank 6, pin F13
Pin 49, BCBUS4	BCBUS4	SC FPGA U18 bank 6, pin F12

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The TEC0850 board is equipped with the FTDI FT601Q USB3 to 32bit-FIFO adapter controller connected to USB-C connector J10 to provide access to the Zynq MPSoC PL HP I/O's of bank 64. Also 13 control signals of the FTDI FT601Q are connected to the HP bank 64.

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title	Table x: SI5345 I2C address19: FT601Q interface connections

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FT601Q U9 Pin	Signal Schematic Name	Connected to	Notes
Pin 40, DATA0	DATA0	PL HP bank 64, pin AK1	user GPIO's
Pin 41, DATA1	DATA1	PL HP bank 64, pin AJ10
Pin 42, DATA2	DATA2	PL HP bank 64, pin AJ9
Pin 43, DATA3	DATA3	PL HP bank 64, pin AK7
Pin 44, DATA4	DATA4	PL HP bank 64, pin AK5
Pin 45, DATA5	DATA5	PL HP bank 64, pin AM1
Pin 46, DATA6	DATA6	PL HP bank 64, pin AL2
Pin 47, DATA7	DATA7	PL HP bank 64, pin AK4
Pin 50, DATA8	DATA8	PL HP bank 64, pin AN1
Pin 51, DATA9	DATA9	PL HP bank 64, pin AL3
Pin 52, DATA10	DATA10	PL HP bank 64, pin AK8
Pin 53, DATA11	DATA11	PL HP bank 64, pin AN2
Pin 54, DATA12	DATA12	PL HP bank 64, pin AP2
Pin 55, DATA13	DATA13	PL HP bank 64, pin AL7
Pin 56, DATA14	DATA14	PL HP bank 64, pin AL5
Pin 57, DATA15	DATA15	PL HP bank 64, pin AM4
Pin 60, DATA16	DATA16	PL HP bank 64, pin AN4
Pin 61, DATA17	DATA17	PL HP bank 64, pin AM5
Pin 62, DATA18	DATA18	PL HP bank 64, pin AM6
Pin 63, DATA19	DATA19	PL HP bank 64, pin AN3
Pin 64, DATA20	DATA20	PL HP bank 64, pin AP3
Pin 65, DATA21	DATA21	PL HP bank 64, pin AP4
Pin 66, DATA22	DATA22	PL HP bank 64, pin AP5
Pin 67, DATA23	DATA23	PL HP bank 64, pin AN6
Pin 69, DATA24	DATA24	PL HP bank 64, pin AN7
Pin 70, DATA25	DATA25	PL HP bank 64, pin AP6
Pin 71, DATA26	DATA26	PL HP bank 64, pin AP7
Pin 72, DATA27	DATA27	PL HP bank 64, pin AP11
Pin 73, DATA28	DATA28	PL HP bank 64, pin AP10
Pin 74, DATA29	DATA29	PL HP bank 64, pin AP9
Pin 75, DATA30	DATA30	PL HP bank 64, pin AN9
Pin 76, DATA31	DATA31	PL HP bank 64, pin AP8
Pin 58, CLK	FIFO_CLK	PL HP bank 64, pin AL6	control signals
Pin 4, BE0	BE_0	PL HP bank 64, pin AM10
Pin 5, BE1	BE_1	PL HP bank 64, pin AK10
Pin 6, BE2	BE_2	PL HP bank 64, pin AM11
Pin 7, BE3	BE_3	PL HP bank 64, pin AL11
Pin 13, nOE	OE_N	PL HP bank 64, pin AL8
Pin 12, nRD	RD_N	PL HP bank 64, pin AK9
Pin 11, nWR	WR_N	PL HP bank 64, pin AM9
Pin 8, nTXE	TXE_N	PL HP bank 64, pin AK12
Pin 9, nRXN	RXF_N	PL HP bank 64, pin AJ12
Pin 10, nSIWU	SIWU_N	PL HP bank 64, pin AL10
Pin 15, nRESET	FTDI_RESET_N	PL HP bank 64, pin AM8
Pin 16, nWAKEUP	WAKEUP_N	PL HP bank 64, pin AN8

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anchor	Figure_18
title	Figure 18: Quad-SPI Flash Memory

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title	Table x: SI5345 I2C address20: Quad-SPI Flash memory interface connections

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IC	Memory Density	MIO	Signal Schematic Name	Flash Memory Pin
QSPI Flash U24, N25Q256A11E1240E	256 Mbit (32 MByte)	0	MIO0	B2
		1	MIO1	D2
		2	MIO2	C4
		3	MIO3	D4
		4	MIO4	D3
		5	MIO5	C2
QSPI Flash U25, N25Q256A11E1240	256 Mbit (32 MByte)	7	MIO7	C2
		8	MIO8	D3
		9	MIO9	D2
		10	MIO10	C4
		11	MIO11	D4
		12	MIO12	B2

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The EEPROMs U63 and U64 are programmable via the on-board I²C bus connected to MIO 20...21 pins. The I²C address is shown in the table below.

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title	Table x21: EEPROMs I2C Addresses

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I2C address	Chip	Description
0x50	U63 24AA128T-I/ST	128K Serial EEPROM
0x53	U64 24AA025E48T-I/OT	2K Serial EEPROM with EUI-48™ or EUI-64™ Node Identity

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title	Figure 20: TEC0850 cPCI USB2 interface

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title	Table x: EEPROMs I2C Addresses22: USB2 ULPI interface description

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PHY Pin	Connected to	Notes
ULPI	PS bank MIO52 ... MIO63	Zynq Ultrascale+ USB0 MIO pins are connected to the PHY
REFCLK	-	52MHz from on board oscillator U12
REFSEL[0..2]	-	All pins set to GND selects the external reference clock frequency (52.000000 MHz)
RESETB	Zynq MPSoC MIO16, pin AM16	Low active USB2 PHY Reset
DP, DM	cPCI connector J1	USB2 data lane
CPEN	-	External USB power switch active-high enable signal
VBUS	5V	Connected to USB VBUS via a series of resistors, see schematic
ID	3.3V	B-device

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The TEC0850 Board has 4 8-bit parallel Texas Instruments THS5641AIPW digital to analog converter (DAC) with up to 100 MSPS update rate connected to TI THS4631D operational amplifiers. See Schematic circuitry and TI THS5641 data sheet for proper operation of the on-board DAC units.

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DAC unit	Signal Schematic Name	Connected to	Functionality
DAC1 U28	DAC1_D0	PL HD bank 50, pin D11	Digital input bits D[7:0] D7 is most significant data bit (MSB), D0 is least significant data bit (LSB).
	DAC1_D1	PL HD bank 50, pin D10
	DAC1_D2	PL HD bank 50, pin G11
	DAC1_D3	PL HD bank 50, pin J11
	DAC1_D4	PL HD bank 50, pin G10
	DAC1_D5	PL HD bank 50, pin H10
	DAC1_D6	PL HD bank 50, pin J10
	DAC1_D7	PL HD bank 50, pin E10
	DAC1_CLK	PL HD bank 50, pin F12	External clock input, input data latched on rising edge of the clock.
	DAC1_MODE	PL HD bank 50, pin F10	Input code format (binary, twos complement)
	EN_DAC1	SC FPGA U18 bank 8, pinE6	generate 3.3V voltages LDO U35, U34
DAC2 U31	DAC2_D0	PL HD bank 50, pin G15	Digital input bits D[7:0] D7 is most significant data bit (MSB), D0 is least significant data bit (LSB).
	DAC2_D1	PL HD bank 50, pin H14
	DAC2_D2	PL HD bank 50, pin J14
	DAC2_D3	PL HD bank 50, pin G14
	DAC2_D4	PL HD bank 50, pin G13
	DAC2_D5	PL HD bank 50, pin H13
	DAC2_D6	PL HD bank 50, pin H12
	DAC2_D7	PL HD bank 50, pin J12
	DAC2_CLK	PL HD bank 50, pin F12	External clock input, input data latched on rising edge of the clock.
	DAC2_MODE	PL HD bank 50, pin F11	Input code format (binary, twos complement)
	EN_DAC2	SC FPGA U18 bank 8, pin E8	generate 3.3V voltages LDO U32, U60
DAC3 U29	DAC3_D0	PL HD bank 44, pin AG14	Digital input bits D[7:0] D7 is most significant data bit (MSB), D0 is least significant data bit (LSB).
	DAC3_D1	PL HD bank 44, pin AE13
	DAC3_D2	PL HD bank 44, pin AG13
	DAC3_D3	PL HD bank 44, pin AJ15
	DAC3_D4	PL HD bank 44, pin AJ14
	DAC3_D5	PL HD bank 44, pin AH14
	DAC3_D6	PL HD bank 44, pin AL13
	DAC3_D7	PL HD bank 44, pin AM13
	DAC3_CLK	PL HD bank 44, pin AK15	External clock input, input data latched on rising edge of the clock.
	DAC3_MODE	PL HD bank 44, pin AK14	Input code format (binary, twos complement)
	EN_DAC3	SC FPGA U18 bank 8, pin B6	generate 3.3V voltages LDO U66, U68
DAC4 U33	DAC4_D0	PL HD bank 44, pin AP14	Digital input bits D[7:0] D7 is most significant data bit (MSB), D0 is least significant data bit (LSB).
	DAC4_D1	PL HD bank 44, pin AN14
	DAC4_D2	PL HD bank 44, pin AM14
	DAC4_D3	PL HD bank 44, pin AN13
	DAC4_D4	PL HD bank 44, pin AP12
	DAC4_D5	PL HD bank 44, pin AN12
	DAC4_D6	PL HD bank 44, pin AF13
	DAC4_D7	PL HD bank 44, pin AH13
	DAC4_CLK	PL HD bank 44, pin AK13	External clock input, input data latched on rising edge of the clock.
	DAC4_MODE	PL HD bank 44, pin AK13	Input code format (binary, twos complement)
	EN_DAC4	SC FPGA U18 bank 8, pin A6	generate 3.3V voltages LDO U70, U72

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