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| Scroll Title |
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| anchor | Table_13 |
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| title | Table 13: Default MIO Configuration |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| PS MIO | Function | Connected to |
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| 0 | SPI0 | U24-B2, CLK |
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| 1 | SPI0 | U24-D2, DO/IO1
|
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| 2 | SPI0 | U24-C4, WP/IO2
|
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| 3 | SPI0 | U24-D4, HOLD/IO3 |
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| 4 | SPI0 | U24-D3, DI/IO0 |
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| 5 | SPI0 | U24-C2, CS |
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| 6 | - | Not connected |
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| 7 | SPI1 | U25-C2, CS |
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| 8 | SPI1 | U25-D3, DI/IO0 |
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| 9 | SPI1 | U25-D2, DO/IO1 |
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| 10 | SPI1 | U17-C4, WP/IO2 |
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| 11 | SPI1 | U25-D4, HOLD/IO3 |
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| 12 | SPI1 | U25-B2, CLK |
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| 13 ... 15 | - | not connected |
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| 16 | USB2 PHY Reset | USB2 PHY U11, pin27 |
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| 17 | - | not used |
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| 18 ... 19 | - | not connected |
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| 20 ...21 | PS MIO I²C | I²C peripherals |
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| 22 ... 25 | user MIO | SC FPGA U18, bank 2 |
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| 26 ... 38 | RGMII | GbE PHY U20 |
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| 39 ... 44 | - | not connected |
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| 45 ... 51 | SD IO | MicroSD Card socket J11 |
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| 52 ... 63 | USB2 ULPI | USB2 PHY U11 |
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| 64 ... 75 | - | not used |
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| 76 ... 77 | ETH MDC / MDIO | GbE PHY U20 |
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|
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| Scroll Title |
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| anchor | Table_18 |
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| title | Table 18: FT2232H interface connections |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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|
| FT2232H U3 Pin | Signal Schematic Name | Connected to | Notes |
|---|
| Pin 12, ADBUS0 | ADBUS0 | SC FPGA U18 bank 6, pin G9
| JTAG interface | | Pin 13, ADBUS1 | ADBUS1 | SC FPGA U18 bank 6, pin F10 | | Pin 14, ADBUS2 | ADBUS2 | SC FPGA U18 bank 6, pin E10 | | Pin 15, ADBUS3 | ADBUS3 | SC FPGA U18 bank 6, pin D9 | | Pin 32, BDBUS0 | BDBUS0 | SC FPGA U18 bank 6, pin B11 | UART and
user configurable GPIO's
| | Pin 33, BDBUS1 | BDBUS1 | SC FPGA U18 bank 6, pin A12 | | Pin 34, BDBUS2 | BDBUS2 | SC FPGA U18 bank 6, pin B12
| | Pin 35, BDBUS3 | BDBUS3 | SC FPGA U18 bank 6, pin C11 | | Pin 37, BDBUS4 | BDBUS4 | SC FPGA U18 bank 6, pin B13 | | Pin 38, BDBUS5 | BDBUS5 | SC FPGA U18 bank 6, pin C12 | | Pin 39, BDBUS6 | BDBUS6 | SC FPGA U18 bank 6, pin C13 | | Pin 40, BDBUS7 | BDBUS7 | SC FPGA U18 bank 6, pin D11 | | Pin 42, BCBUS0 | BCBUS0 | SC FPGA U18 bank 6, pin D12 | | Pin 46, BCBUS1 | BCBUS1 | SC FPGA U18 bank 6, pin E13 | | Pin 47, BCBUS2 | BCBUS2 | SC FPGA U18 bank 6, pin E12 | | Pin 48, BCBUS3 | BCBUS3 | SC FPGA U18 bank 6, pin F13 | | Pin 49, BCBUS4 | BCBUS4 | SC FPGA U18 bank 6, pin F12 | | Pin 11, nRESET | FTDI_RST | SC FPGA U18 bank 6, pin E9 | control signals |
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FT601Q
The TEC0850 board is equipped with the FTDI FT601Q USB3 to 32bit-FIFO adapter controller connected to USB-C connector J10 to provide access to the Zynq MPSoC PL HP I/O's of bank 64. Also 13 control signals of the FTDI FT601Q are connected to the HP bank 64.
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